Technology for lowering instantaneous power consumption of neural processing unit
AssigneeDeepx Co., Ltd.
InventorsLok Won Kim, Jung Boo Park, Seong Jin Lee
Life of this patent
Estimating the term…
Abstract
A system may comprise a neural processing unit (NPU) including at least one memory and a plurality of processing elements (PEs) capable of performing operations for at least one artificial neural network (ANN) model. The plurality of PEs may include an adder, a multiplier, and an accumulator. The plurality of PEs may include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal.
Claims18
A system comprising:
- a neural processing unit (NPU) including at least one memory and a plurality of processing elements (PEs) capable of performing operations for at least one artificial neural network (ANN) model,
- wherein the plurality of PEs include an adder, a multiplier, and an accumulator,
- wherein the plurality of PEs include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal, and
- wherein a reference phase of the second group of PEs is based on a conversion from the first portion to the second portion of the clock signal.
A system on chip (SoC) comprising:
- a first circuit arranged as at least one memory;
- and
- a second circuit arranged as a plurality of processing elements (PEs) capable of performing operations for at least one of artificial neural network (ANN) models,
- wherein the plurality of PEs include an adder, a multiplier, and an accumulator,
- wherein the plurality of PEs include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal, and
- wherein a reference phase of the second group of PEs is based on a conversion from the first portion to the second portion of the clock signal.
A method of operating a neural processing unit (NPU) comprising:
- generating a clock signal for driving the NPU including a plurality of processing elements (PEs);
- operating a first group of PEs of the plurality of PEs on a first portion of the clock signal;
- and
- operating a second group of PEs of the plurality of PEs on a second portion of the clock signal,
- wherein a reference phase of the second group of PEs is based on a conversion from the first portion to the second portion of the clock signal, and
- wherein the plurality of PEs include an adder, a multiplier, and an accumulator.
Dependencies are inferred from the claim text.