A positive feedback latch amplitude limiting control circuit of a passive radio frequency identification (RFID) tag, the circuit comprising a signal generating circuit, a first signal processing circuit, a first discharge circuit, a second signal processing circuit, a second signal control circuit and a second discharge circuit, wherein:
- the signal generating circuit is connected between an output terminal of a rectifier circuit and ground, and is configured to:
- generate a first control signal S1 that varies with change of strength of a magnetic field coupled to a coil of the passive RFID tag, input the first control signal S1 to the first signal processing circuit, the first discharge circuit, and the second signal processing circuit, and receive a logic signal S2 returned by the first signal processing circuit;
- the first signal processing circuit is connected between the output terminal of the rectifier circuit and the ground, and is configured to:
- receive the first control signal S1, latch the first control signal S1 to a high level or a low level according to a voltage amplitude of the first control signal S1, obtain the processed logic signal S2, and return the logic signal S2 to the signal generating circuit;
- the first discharge circuit includes a MOS transistor whose gate voltage is indirectly controlled by a latch, and source and drain thereof are respectively connected between the output terminal of the rectifier circuit and the ground, wherein:
- when the strength of the magnetic field coupled to the coil of the passive RFID tag is less than a preset value, the first control signal S1 is pulled down to the ground to maintain the first discharge circuit in a turned-off state;
- when the strength of the coupled magnetic field is greater than the preset value, the first control signal S1 is set to a high level to turn on the discharge circuit, and charges at the output terminal of the rectifier circuit are outputted to the ground;
- and an internal positive feedback latch mechanism of the latch makes the first control signal S1 have a substantially strong pull-down driving force when being pulled to a low level, such that a control gate of the discharge path is fully turned off, which avoids the discharge state of a sub-threshold region;
- the second signal processing circuit is connected between the output terminal of the rectifier circuit and the ground, and is configured to:
- receive the first control signal S1, latch the first control signal S1 to the high level or the low level according to the voltage amplitude of the first control signal S1, obtain a processed logic signal S2′, and input the logic signal S2′ to the second signal control circuit;
- the second signal control circuit is connected between the output terminal of the rectifier circuit and the ground, and is configured to:
- generate a second control signal S3 according to the high-level or low-level of the logic signal S2′, and input the second control signal S3 to the second discharge circuit;
- the second discharge circuit includes a MOS transistor whose gate voltage is indirectly controlled by the latch, and source and drain thereof are respectively connected between the output terminal of the rectifier circuit and the ground, wherein:
- when the strength of the magnetic field coupled to the coil of the passive RFID tag is less than a preset value, the first control signal S1 is pulled down to the ground to maintain the discharge circuit in the turned-off state;
- when the strength of the coupled magnetic field is greater than the preset value, the first control signal S1 is set to a high level to turn on the discharge circuit, and the charges at the output terminal of the rectifier circuit are outputted to the ground;
- and an internal positive feedback latch mechanism of the latch makes the first control signal S1 have a substantially strong pull-down driving force when being pulled to the low level, such that a control gate of the discharge path is fully turned off, which avoids the discharge state of the sub-threshold region;
- and
- the first signal processing circuit includes a capacitive device connected to the ground, a first inverting sub-module INV1 and a second inverting sub-module INV2, wherein a positive terminal of the capacitive device is connected to a latch flip-flop with positive feedback characteristic formed by connecting an output terminal of the first inverting sub-module INV1 and an input terminal of the second inverting sub-module INV2, and connecting an input terminal of the first inverting sub-module INV1 and an output terminal of the second inverting sub-module INV2;
- and the second signal processing circuit includes a detector circuit formed by at least one unidirectional conduction threshold device and a capacitive device, a third inverting sub-module INV3 and a fourth inverting sub-module INV4, wherein an output terminal of the detector circuit is connected to a latch flip-flop with positive feedback characteristic formed by connecting an output terminal of the third inverting sub-module INV3 and an input terminal of the fourth inverting sub-module INV4, and connecting an input terminal of the third inverting sub-module INV3 and an output terminal of the fourth inverting sub-module INV4.