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US 11,893,419 B2Granted
Hardware accelerators using shared interface registers
AssigneeApple Inc.
InventorMahesh B. Chappalli
Life of this patent
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Abstract
Methods and systems include processors and hardware accelerators. The processor initiates a first process in a first hardware accelerator configured to aid the processor in performing the first process. The processor initiates the first process using one or more interface registers. The processor performs additional processing while the first hardware accelerator performs the first process after initiation of the first process. The processor also initiates a second process in a second hardware accelerator configured to aid the processor in performing a second process. Moreover, the processor initiates the second process using the one or more interface registers.
Claims19
A method, comprising:
- using a processor, initiating a first process in a first hardware accelerator configured to aid the processor by performing the first process, wherein initiating the first process comprises using one or more interface registers, and wherein the one or more interface registers comprises an accelerator identifier register that is used to uniquely identify the first hardware accelerator, a second hardware accelerator, and a third hardware accelerator;
- using the processor, performing additional processing while the first hardware accelerator performs the first process after the processor initiates the first process and before the first process is completed;
- using the processor, initiating a second process in the second hardware accelerator configured to aid the processor by performing the second process, wherein initiating the second process comprises using the one or more interface registers;
- using the processor, initiating a third process in the third hardware accelerator configured to aid the processor in performing the third process, wherein the third hardware accelerator comprises a blocking accelerator that aids in the third process without using the one or more interface registers other than the accelerator identifier register;
- and
- receiving, at the processor, an indication via the one or more interface registers to indicate that the first hardware accelerator has completed the first process and that the processor is to operate on results from the first process.
3 more elements
An electronic device comprising:
- a first hardware accelerator configured to assist in performing processes of a first type;
- a second hardware accelerator configured to assist in performing processes of a second type;
- a third hardware accelerator configured to assist in performing processes of a third type;
- a plurality of interface registers accessible by both the first and second hardware accelerators, wherein the first and second hardware accelerators are non-blocking accelerators that use the plurality of interface registers, and the third hardware accelerator is a blocking accelerator that does not use the plurality of interface registers other than an accelerator identifier register to assist in performing processes of the third type;
- a processor configured to execute instructions configured to cause the processor to:
- initiate a first process of the first type in the first hardware accelerator using the plurality of interface registers;
- perform additional processing while the first hardware accelerator performs the first process after the first process is initiated;
- initiate a second process of the second type in the second hardware accelerator using the plurality of interface registers;
- and
- receive an indication via the plurality of interface registers to indicate that the first hardware accelerator has completed the first process and that the processor is to operate on results from the first process.
7 more elements
A method comprising:
- receiving an indication that a process is to be performed at a non-blocking accelerator from a processor at an interface register of a plurality of interface registers for a plurality of non-blocking accelerators;
- in response to the indication, causing the non-blocking accelerator to enter an idle state;
- in the idle state, receiving a run indication from the processor, wherein the run indication indicates that the process at the non-blocking accelerator is to be started, wherein the indication comprises a value in a run register of the plurality of interface registers;
- based at least in part on the run indication, entering a busy state and beginning the process in the non-blocking accelerator while the processor is configured to perform other processing while the process is completed;
- in the busy state, causing the non-blocking accelerator to change from the busy state to the idle state and to raise a completion indication of the plurality of interface registers to indicate that the process has been completed;
- and
- causing a second process to be started in a blocking hardware accelerator, wherein the blocking accelerator aids in the second process without using the plurality of interface registers other than an accelerator identifier register.
4 more elements
Dependencies are inferred from the claim text.