Computational array microprocessor system with hardware arbiter managing memory requests
AssigneeTesla, Inc.
InventorsEmil Talpes, Peter Joseph Bannon, Kevin Altair Hurd
Life of this patent
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Abstract
A microprocessor system comprises a computational array and a hardware arbiter. The computational array includes a plurality of computation units. Each of the plurality of computation units operates on a corresponding value addressed from memory. The hardware arbiter is configured to control issuing of at least one memory request for one or more of the corresponding values addressed from the memory for the computation units. The hardware arbiter is also configured to schedule a control signal to be issued based on the issuing of the memory requests.
Claims20
A microprocessor system, comprising:
- a computational array that includes a plurality of computation units, wherein each of the plurality of computation units operates on a corresponding value addressed from memory, and wherein the computational array is configured to perform a convolution operation associated with weight data and input data;
- and
- a hardware arbiter configured to manage memory requests, wherein the hardware arbiter is configured to queue a first portion of the memory requests in a first queue corresponding to weight data and a second portion of the memory requests in a second queue corresponding to input data, wherein the hardware arbiter is configured to prioritize a first individual memory request from one of the first queue and second queue over a second individual memory request from the other of the first queue and second queue, and wherein the second individual memory request was received earlier than the first individual memory request,
- wherein the hardware arbiter is in communication with a control queue configured to queue operations, and wherein the hardware arbiter is configured to trigger a particular operation of one or more computation units in the plurality of computation units on a subset of the corresponding values based on the hardware arbiter granting memory access for the subset of the corresponding values.
A method implemented by a microprocessor system, the method comprising:
- receiving an operation for a computational array, wherein the computational array includes a hardware arbiter and a plurality of computation units, wherein each of the plurality of computation units operates on a corresponding value addressed from memory, and wherein the operation is queued in a control queue and causes performance of one or more convolutions associated with weight data and input data;
- causing, by the hardware arbiter, a plurality of memory requests associated with the operation to be queued in a single queue, the memory requests being for a subset of the corresponding values, wherein the memory requests are queued with respective metadata identifying, at least, that the memory requests are for weight data or input data, wherein the hardware arbiter is configured to dequeue a particular of the memory requests out-of-order based on a priority associated with the metadata queued with the particular of the memory request;
- and
- triggering, by the hardware arbiter using a control signal, the operation based on granting of the memory requests, wherein the control signal triggers dequeuing of the operation from the control queue.
Dependencies are inferred from the claim text.