Multi-processor system and method for processing floating point operation thereof
AssigneeElectronics and Telecommunications Research Institute
InventorsJu-Yeob Kim, Jin Ho Han
Life of this patent
Estimating the term…
Abstract
A method for processing floating point operations in a multi-processor system including a plurality of single processor cores is provided. In this method, upon receiving a group setting for performing an operation, the plurality of single processor cores are grouped into at least one group according to the group setting, and a single processor core set as a master in the group loads an instruction for performing the operation from an external memory, and performs parallel operations by utilizing floating point units (FUPs) of all single processor cores in the group according to the instructions.
Claims11
A method for processing floating point operations in a multi-processor system including a plurality of single processor cores, the method comprising:
- receiving a group setting for performing an operation;
- when the plurality of single processor cores are grouped into at least one group according to the group setting, loading, by a single processor core that is set as a master among single processor cores in a group of the at least one group, instructions for performing the operation from an external memory;
- and
- performing, by the single processor core that is set as the master, parallel operations on data to be operated by using floating point units (FPUs) of all single processor cores in the group according to the instructions.
A multi-processor system for processing floating point operation, the multi-processor system comprising
- a plurality of single processor cores including a controller and a floating point unit (FPU),
- wherein a controller of a single processor core that is set as a master in any one group in which two or more single processor cores are grouped according to a group setting for performing the operation loads instructions for performing the operation, and performs parallel operations on data to be operated by utilizing FPUs of other single processor cores in the any one group according to the instructions.
Dependencies are inferred from the claim text.