Systems and methods for performing 16-bit floating-point matrix dot product instructions

A system on a chip (SoC) comprising:

• a memory controller;
• and
• a general-purpose central processing unit (CPU) core coupled with the memory controller, the general-purpose CPU core comprising:
• a control register to specify a round mode;
• fetch circuitry to fetch an instruction;
• decode circuitry to decode the instruction, the instruction having a first field to specify a first storage location of a plurality of data elements corresponding to a first matrix having M rows by N columns of 32-bit single precision floating-point data elements, a second field to specify a second storage location of a plurality of data elements corresponding to a second matrix having M rows by K columns of 16-bit floating-point data elements having a bfloat16 format, and a third field to specify a third storage location of a plurality of data elements corresponding to a third matrix having K rows by N columns of 16-bit floating-point data elements having the bfloat16 format;
• and
• execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the instruction to, for each row m of the M rows of the second matrix, and for each column n of the N columns of the third matrix:
• convert K 16-bit floating-point data elements corresponding to the row m of the second matrix to K 32-bit floating-point data elements, and convert K 16-bit floating-point data elements corresponding to the column n of the third matrix to K 32-bit floating-point data elements;
• generate two dot products from the K 32-bit floating-point data elements corresponding to the row m of the second matrix and the K 32-bit floating-point data elements corresponding to the column n of the third matrix, including performing floating point rounding;
• accumulate the two dot products with a 32-bit floating-point data element corresponding to a row m of the M rows, and corresponding to a column n of the N columns, of the first matrix, including performing floating point rounding, to generate a result 32-bit single precision floating-point data element;
• and
• store the result 32-bit floating-point data element in a position of the first storage location corresponding to the row m and the column n of the first matrix.

A system comprising:

• a memory;
• and
• a general-purpose central processing unit (CPU) core coupled with the memory, the general-purpose CPU core comprising:
• a control register to specify a round mode;
• fetch circuitry to fetch an instruction;
• decode circuitry to decode the instruction, the instruction having a first field to specify a first storage location of a plurality of data elements corresponding to a first matrix having M rows by N columns of 32-bit single precision floating-point data elements, a second field to specify a second storage location of a plurality of data elements corresponding to a second matrix having M rows by K columns of 16-bit floating-point data elements having a bfloat16 format, and a third field to specify a third storage location of a plurality of data elements corresponding to a third matrix having K rows by N columns of 16-bit floating-point data elements having the bfloat16 format;
• and
• execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the instruction to, for each row m of the M rows of the second matrix, and for each column n of the N columns of the third matrix:
• convert K 16-bit floating-point data elements corresponding to the row m of the second matrix to K 32-bit floating-point data elements, and convert K 16-bit floating-point data elements corresponding to the column n of the third matrix to K 32-bit floating-point data elements;
• generate two dot products from the K 32-bit floating-point data elements corresponding to the row m of the second matrix and the K 32-bit floating-point data elements corresponding to the column n of the third matrix, including performing floating point rounding;
• accumulate the two dot products with a 32-bit floating-point data element corresponding to a row m of the M rows, and corresponding to a column n of the N columns, of the first matrix, including performing floating point rounding, to generate a result 32-bit single precision floating-point data element;
• and
• store the result 32-bit floating-point data element in a position of the first storage location corresponding to the row m and the column n of the first matrix.

A chip comprising:

• a plurality of central processing unit (CPU) cores, including a CPU core comprising:
• a control register to specify a round mode;
• decode circuitry, the decode circuitry to decode an instruction, the instruction to specify a first storage location of a plurality of data elements corresponding to a first matrix having M rows by N columns of 32-bit single precision floating-point data elements, to specify a second storage location of a plurality of data elements corresponding to a second matrix having M rows by K columns of 16-bit floating-point data elements having a bfloat16 format, and to specify a third storage location of a plurality of data elements corresponding to a third matrix having K rows by N columns of 16-bit floating-point data elements having the bfloat16 format;
• and
• execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the instruction to, for each row m of the M rows of the second matrix, and for each column n of the N columns of the third matrix:
• generate a dot product from K 16-bit floating-point data elements corresponding to the row m of the second matrix and K 16-bit floating-point data elements corresponding to the column n of the third matrix;
• accumulate the dot product with a 32-bit single precision floating-point data element corresponding to a row m of the M rows, and corresponding to a column n of the N columns, of the first matrix, including application of a single round to nearest even round mode regardless of the round mode specified by the control register to generate a result 32-bit single precision floating-point data element;
• and
• store the result 32-bit single precision floating-point data element in a position of the first storage location corresponding to the row m and the column n of the first matrix.