Process for a floating point dot product multiplier-accumulator

A process for a pipelined floating point multiplier-accumulator (MAC) implemented with registers separating stages and configured to generate a sum of N products from a corresponding pair of values, each pair of values comprising a floating point input value and a corresponding floating point coefficient value, the process comprising:

• each of the N products provided by a dot product controller performing a respective dot product process of:
• outputting a sign bit computed from an exclusive OR (XOR) of a sign bit of a floating point input value with a sign bit of a corresponding floating point coefficient value;
• computing an exponent sum of an exponent of the floating point input value with an exponent of the corresponding floating point coefficient, determining a maximum exponent (MAX_EXP) value from all N exponent sums, determining an exponent difference (EXP_DIFF) value between the MAX_EXP value and the corresponding exponent sum;
• generating a product by multiplying a mantissa from the floating point input value with a mantissa from the corresponding floating point coefficient value and normalizing the product, and asserting an exponent increment (EXP_INC) bit if an overflow results from the multiplication;
• when the EXP_DIFF value is 0 and the EXP_INC bit is asserted, incrementing MAX_EXP and asserting a maximum increment (MAX_INC) bit;
• when the EXP_DIFF value is not 0 and the EXP_INC bit is not asserted and the MAX_INC bit is asserted, incrementing the EXP_DIFF value;
• when the EXP_DIFF value is not 0 and the EXP_INC bit is asserted and the MAX_INC bit is not asserted, decrementing the EXP_DIFF value;
• prepending and appending 0 values to the normalized product to generate a padded value, modifying the padded value by taking a two's complement of the padded value if the sign bit is 1, thereafter right shifting the result by the EXP_DIFF value to generate an integer form fraction;
• a summing process receiving each of the N integer form fractions and outputting an integer form fraction sum;
• converting the integer form fraction sum to a resulting sign bit and resulting normalized mantissa, and outputting a floating point output value comprising the resulting sign bit, an exponent derived from said MAX_EXP value, and the resulting normalized mantissa.

A process for a pipelined floating point multiplier-accumulator (MAC) receiving N pairs of floating point values, each pair comprising a floating point input and a floating point coefficient, each floating point input and floating point coefficient comprising a sign bit, a plurality of mantissa bits, and a plurality of exponent bits, the process configured to operate on at least one pipeline stage register and comprising:

• identifying for each of the N pairs of floating point values a maximum exponent sum (MAX_EXP) value among N sums of input exponent and coefficient exponent bits;
• outputting for each of the N pairs of floating point values an exclusive OR bit value of a sign bit of an input value and a sign bit of a corresponding coefficient value to the at least one pipeline stage register;
• for each of the N pairs of floating point values, forming an integer multiplication product of mantissa bits of a corresponding floating point input value and mantissa bits of a corresponding floating point coefficient value, the integer multiplication product rounded and normalized to a fewer number of bits, thereby forming a normalized multiplication result to the at least one pipeline stage register, and asserting the EXP_INC bit if the most significant bit of the integer multiplication product is 1;
• for each of the N pairs of floating point values, generating an exponent difference (EXP_DIFF) value as a difference between the MAX_EXP value and the sum of an exponent of a floating point input value and an exponent of a corresponding floating point coefficient value;
• when the EXP_DIFF value is 0 and the EXP_INC bit is asserted, incrementing MAX_EXP and asserting a maximum increment (MAX_INC) bit;
• when the EXP_DIFF value is not 0 and the EXP_INC bit is not asserted and the MAX_INC bit is asserted, incrementing the EXP_DIFF value;
• when the EXP_DIFF value is not 0 and the EXP_INC bit is asserted and the MAX_INC bit is not asserted, decrementing the EXP_DIFF value;
• for each of the N pairs of floating point values, performing a padding step of padding the normalized multiplication result to a greater number of bits than a number of bits in the normalized multiplication result to form a padded value, performing a complement step of replacing the padded value with a 2s complement of the padded value if a respective sign bit for the associated pair of floating point values is 1, and performing a shift step of shifting a result of the complement step by a number EXP_DIFF of bit positions to generate an integer form fraction value;
• computing a sum of N integer form fraction values;
• generating a floating point result by determining a sign of the adder stage sum to generate a resulting sign part, normalizing the sum to generate a resulting mantissa part, and generating the floating point result from the resulting sign part, an exponent derived from the MAX_EXP value, and the resulting mantissa part.