Method for optimizing floor plan for an integrated circuit

A method, comprising:

• calculating a channel width of each of a plurality of channels interposed between a plurality of macros based on area of buffers inserted in the plurality of channels;
• separating the plurality of macros based on a largest width of the channel widths of the plurality of channels to form an interposed channel;
• and
• forming the plurality of macros aligned with first and second boundaries of the interposed channel and are coupled thereto through pins of the plurality of macros.

A method, comprising:

• forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros;
• and
• forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a register,
• wherein the first group of macros and the second group of macros in a floor plan are formed according to a plurality of weights of the first group of macros and the second group of macros.