Hybrid sheet layout, method, system, and structure

A method of generating an integrated circuit (IC) layout diagram, the method comprising:

• abutting a first row of cells with a second row of cells along a border, the first row of cells comprising first and second active sheets extending along a row direction, the second row of cells comprising third and fourth active sheets extending along the row direction;
• aligning the border along a first metal track of a plurality of metal tracks having a metal track pitch;
• and
• overlapping each of the first through fourth active sheets with a corresponding first through fourth back-side via region,
• wherein
• each of the first through fourth active sheets and first through fourth back-side via regions has a width in a width direction perpendicular to the row direction, the width having a width value,
• the width value of the first active sheet is greater than that of the third active sheet,
• the width value of the first back-side via region is greater than that of the third back-side via region,
• a distance from the first active sheet to the border has a value less than a minimum spacing rule for metal-like defined regions of a manufacturing process corresponding to the IC layout diagram,
• each of the first and second rows of cells has a height in the width direction equal to five times the metal track pitch, and
• at least one of the abutting the first row of cells with the second row of cells or the overlapping the first through fourth active sheets with the first through fourth back-side via regions is performed by a processor.

A method of generating an integrated circuit (IC) layout diagram, the method comprising:

• abutting a first row of cells with a second row of cells along a border, the first row of cells comprising first and second active sheets extending along a row direction, the second row of cells comprising third and fourth active sheets extending along the row direction;
• and
• overlapping each of the first through fourth active sheets with a corresponding first through fourth back-side via region,
• wherein
• each of the first through fourth active sheets and first through fourth back-side via regions has a width in a width direction perpendicular to the row direction, the width having a width value,
• a single width value of each of the first and second active sheets is greater than a single width value of the third and fourth active sheets,
• a single width value of each of the first and second back-side via regions is greater than a single width value of each of the third and fourth back-side via regions,
• a distance from the first active sheet to the border has a value less than a minimum spacing rule for metal-like defined regions of a manufacturing process corresponding to the IC layout diagram, and
• at least one of the abutting the first row of cells with the second row of cells or the overlapping the first through fourth active sheets with the first through fourth back-side via regions is performed by a processor.