Allocation of a buffer located in system memory into a cache memory

A method, comprising:

• allocating, by a processing circuit, a plurality of locations in a system memory to a buffer;
• issuing, by the processing circuit, a plurality of memory transactions in a particular order, different from a linear order, for allocating respective locations of the plurality of locations into a cache memory circuit;
• in response to receiving, in the particular order, content from respective ones of the plurality of memory transactions, attempting to cache, by the cache memory circuit, the plurality of locations of the buffer;
• tracking a cache miss rate associated with use of the particular order to cache the plurality of locations;
• and
• in response to determining that the tracked cache miss rate satisfies a threshold rate, adjusting the particular order for a subsequent use.

An apparatus, comprising:

• a system memory circuit;
• a cache memory circuit;
• and
• a processing circuit configured to:
• allocate a portion of the system memory circuit to a buffer having a plurality of storage locations;
• and
• issue a plurality of memory transactions in a particular order, different from a linear order, to allocate respective storage locations of the plurality of storage locations into the cache memory circuit;
• and
• wherein the cache memory circuit is configured to:
• in response to receiving, in the particular order, content from respective ones of the plurality of memory transactions, cache at least a subset of the plurality of storage locations of the buffer in the cache memory circuit;
• track a cache miss rate in the cache memory circuit for memory transactions that include accesses to the plurality of storage locations;
• and
• in response to a determination that the tracked cache miss rate satisfies a threshold rate, modify the particular order.