Analog dot product multiplier
AssigneeCeremorphic, Inc.
InventorsAravinth Kumar Ayyappannair Radhadevi, Sesha Sairam Regulagadda
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Abstract
A dot product multiplier for matrix operations for an A matrix of order 1×m with a coefficient B matrix of order m×m. Processing Elements (PEs) are arranged in an m×m array, the columns of the array summed to provide a dot product result. Each of the PEs contains a sign determiner and a plurality of analog multiplier cells, one multiplier cell for each value bit. The multipliers operate over four clock cycles, initializing a capacitor charge according to sign on a first clock phase, sharing charge on a second phase, canceling charge on a third phase, and outputting the resultant charge on a fourth phase, the resultant charge on each column representing the dot product for that column.
Claims15
A dot product multiplier for multiplying a 1×m A matrix with an m×m B matrix to form a dot product, each element of the A matrix and each element of the B matrix comprising a sign bit and value bits, the dot product multiplier comprising:
- a clock generator providing four non-overlapping phases of clock per clock cycle, the four phases being PH1, PH2, PH3, PH4;
- a plurality of processing elements arranged in said m columns and said m rows, each processing element receiving an ‘a’ element of the A matrix and a ‘b’ element of the B matrix and generating a processing element output;
- each processing element comprising:
- a sign voltage source providing a sign voltage which is a positive voltage for positive multiplication results and a comparatively negative voltage for negative multiplication results based on a sign bit of the ‘a’ element and sign bit of the ‘b’ element;
- a bit multiplier for each particular ‘a’ element value bit an and each ‘b’ element value bit bn, each bit multiplier having an output, the bit multiplier comprising:
- a capacitor having a capacitance Cref*2n, the capacitor initialized to the sign voltage during the first clock phase PH1 if an=1, and initialized to 0V if an=0;
- the bit multiplier coupling the capacitor to capacitors of other bit multipliers during the second clock phase PH2;
- the bit multiplier zeroing the charge on the capacitor if bn=0 on the third clock phase PH3;
- the bit multiplier coupling the capacitor of the bit multiplier to the processing element output during the fourth phase PH4;
- each of the m columns having an accumulator, the accumulator receiving a transferred charge from the bit multiplier outputs in a respective column during the fourth phase PH4;
- each accumulator converting the transferred charge to a digital value indicating a dot product value for an associated column.
A process for forming dot products of a 1×m A matrix with an m×m B matrix, the process operative on an m column and m row array of processing elements (PE), the A matrix having ‘a’ elements and the B matrix having ‘b’ elements, each ‘a’ element and each ‘b’ element comprising a sign bit and n value bits, each processing element comprising a sign voltage source and a plurality n of multipliers, each multiplier operative on a unique value bit an of a value of the A matrix and a value bit of the B matrix, the process comprising:
- charging a multiplier capacitor in each multiplier to a sign voltage provided by the sign voltage source during a first clock phase PH1 if a corresponding bit an is 1;
- sharing capacitor charge across all multiplier capacitors during a second clock phase PH2;
- clearing a charge from the multiplier capacitor if a value bit bn of the B matrix is 0 during a third clock phase PH3;
- connecting all processing element multiplier capacitors of each column together and converting the charge of each column to a digital output value during a fourth clock phase PH4.
Dependencies are inferred from the claim text.