Synchronization mechanisms for a multi-core processor using wait commands having either a blocking or a non-blocking state
AssigneeArm Limited
InventorsAaron Debattista, Jared Corey Smolens
Life of this patent
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AssigneeArm Limited
InventorsAaron Debattista, Jared Corey Smolens
Estimating the term…
Systems, apparatuses and methods suitable for optimizing synchronization mechanisms for multi-core processors are provided. The synchronizing mechanisms may be optimized by receiving a command stream which comprises a plurality of commands including one or more wait commands, wherein each wait command has an associated state and one or more associated conditions; sequentially processing each command in the command stream until a wait command is reached; checking the state associated with the wait command to be processed, wherein if said state is a blocking state, further processing of commands in the command stream is paused until each of said wait command's associated conditions are met, and wherein if said state is a non-blocking state, the next command in the command stream is retrieved and processed.
A method for synchronising processing in a multi-core processor, comprising:
A control unit arranged to:
A system comprising:
Dependencies are inferred from the claim text.