System and method for bypass memory read request detection

A method for reading a memory device, the method comprising:

• receiving a plurality of Compute Express Link (CXL) flow control units (flits) at a physical layer of a CXL memory controller;
• transmitting each of the received plurality of CXL flits to read bypass detection logic of the CXL memory controller;
• analyzing each of the received and transmitted plurality of CXL flits at the read bypass detection logic to identify a bypass memory read request from the plurality of CXL flits, wherein the bypass memory read request comprises an address space;
• transmitting the bypass memory read request over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller;
• discarding the bypass memory read request at the transaction/application layer when the address space of the bypass memory read request is not valid;
• when a read request queue of the CXL memory controller is empty, generating a memory read command on an interface of a memory device attached to the CXL memory controller in response to the bypass memory read request received at the transaction/application layer of the CXL memory controller and when the read request queue of the CXL memory controller is not empty, discarding the bypass memory read request;
• receiving read data from the memory device at the transaction/application layer in response to the memory read command;
• and
• when there is a link layer memory read request at the transaction/application layer that matches the bypass memory read request that generated the memory read command, forwarding the read data received at the transaction/application layer to the link layer of the CXL memory controller and when there is not a link layer memory read request at the transaction/application layer that matches the bypass memory read request that generated the memory read command, discarding the read data received at the transaction/application layer.

A compute express link (CXL) memory controller comprising:

• read bypass detection logic to receive a plurality of CXL flits from a CXL physical layer of a CXL memory controller and to analyze each of the received plurality of CXL flits to identify a bypass memory read request from the plurality of CXL flits;
• a read request bypass path comprising the read bypass detection logic, the read request bypass path connecting the CXL physical layer to a transaction/application layer of the CXL memory controller, the read request bypass path bypassing an arbitration/multiplexing layer of the CXL memory controller and a link layer of the CXL memory controller;
• the transaction/application layer to:
• generate a memory read command on an interface of a memory device associated with the CXL memory controller in response to the bypass memory read request received at the transaction/application layer when a read request queue is empty;
• receive read data from the memory device in response to the memory read command;
• and
• forward the read data received at the transaction/application layer to the link layer when there is a link layer memory read request at the transaction/application layer that matches the bypass memory read request that generated the memory read command.