No-locality hint vector memory access processors, methods, systems, and instructions

A processor comprising:

• a cache hierarchy, the cache hierarchy including a level one (L1) cache and a level two (L2) cache;
• a decode unit to decode a scatter instruction, the scatter instruction having a first field to specify a first source vector register, a second field to specify a source predicate register, a third field to specify a source general-purpose register, and a fourth field to specify a second source vector register, the first source vector register to store a first source vector operand, the first source vector operand having a plurality of first source data elements, the source predicate register to store a source predicate operand, the source predicate operand having a plurality of predicate elements, each predicate element corresponding to a first source data element of the first source vector operand, and corresponding to a data element position in the second source vector register, in a same relative position, and the source general-purpose register to store memory address information;
• and
• execution circuitry coupled with the decode unit, the execution circuitry to execute the decoded scatter instruction, to:
• perform, for those of the predicate elements of a first value, corresponding store operations from data element positions in the second source vector register corresponding to those of the predicate elements of the first value, to store data elements into memory locations derived from the memory address information and first source data elements corresponding to those of the predicate elements of the first value, wherein the store operations are performed with hints that the stored data elements are either not to be cached in the cache hierarchy or are to be prioritized for eviction from the cache hierarchy;
• and
• not write to memory locations derived from the memory address information and first source data elements corresponding to those of the predicate elements of a second value.

A system comprising:

• an integrated memory controller unit;
• and
• a processor core coupled to the integrated memory controller unit, the processor core comprising:
• a cache hierarchy, the cache hierarchy including a level one (L1) cache and a level two (L2) cache;
• a decode unit to decode a non-temporal locality scatter instruction, the non-temporal locality scatter instruction having a first field to specify a first source vector register, a second field to specify a source predicate register, a third field to specify a source general-purpose register, and a fourth field to specify a second source vector register, the first source vector register to store a first source vector operand, the first source vector operand having a plurality of first source data elements, the source predicate register to store a source predicate operand, the source predicate operand having a plurality of predicate elements, each predicate element corresponding to a first source data element of the first source vector operand, and corresponding to a data element position in the second source vector register, in a same relative position, and the source general-purpose register to store memory address information;
• and
• execution circuitry coupled with the decode unit, the execution circuitry to execute the decoded non-temporal locality scatter instruction, to:
• perform, for those of the predicate elements of a first value, corresponding store operations from data element positions in the second source vector register corresponding to those of the predicate elements of the first value, to store data elements into memory locations derived from the memory address information and first source data elements corresponding to those of the predicate elements of the first value;
• and
• not write to memory locations derived from the memory address information and first source data elements corresponding to those of the predicate elements of a second value.