Loading logical to physical mapping table to cache of memory controller
AssigneeYangtze Memory Technologies Co., Ltd.
InventorHua Tan
Life of this patent
Estimating the term…
Abstract
A data operation method of a memory system is provided. The method includes, based on an obtained logical to physical mapping table, determining whether address values of a plurality of target physical addresses in the logical to physical mapping table corresponding to a plurality of target logical addresses are continuous; if so, selecting one of the plurality of target physical addresses as a base physical address, and setting a base physical address offset based on address values of remaining target physical addresses; and storing the base physical address and the base physical address offset into a cache of a memory controller, as a mapping relationship of the plurality of target logical addresses corresponding to the plurality of target physical addresses.
Claims20
A data operation method of a memory system, comprising:
- based on an obtained logical to physical mapping table, determining whether address values of a plurality of target physical addresses in the obtained logical to physical mapping table corresponding to a plurality of target logical addresses are continuous;
- if so, selecting one of the plurality of target physical addresses as a base physical address, and setting a base physical address offset based on address values of remaining target physical addresses;
- and
- storing the base physical address and the base physical address offset into a cache of a memory controller, as a mapping relationship of the plurality of target logical addresses corresponding to the plurality of target physical addresses.
A memory controller, comprising:
- a processing unit;
- a cache corresponding to the processing unit;
- an acceleration determining circuit configured to:
- based on an obtained logical to physical mapping table, determine whether address values of a plurality of target physical addresses in the obtained logical to physical mapping table corresponding to a plurality of target logical addresses are continuous;
- wherein the processing unit is configured to:
- obtain, from the acceleration determining circuit, a first instruction indicating that the address values of the plurality of target physical addresses are determined to be continuous;
- based on the first instruction, select one of the plurality of target physical addresses as a base physical address, and set a base physical address offset based on address values of remaining target physical addresses;
- and
- store the base physical address and the base physical address offset into the cache, as a mapping relationship of the plurality of target logical addresses corresponding to the plurality of target physical addresses.
A memory system, comprising:
- one or more memory devices;
- and
- a memory controller coupled to the memory devices, wherein the memory controller comprises:
- a processing unit;
- a cache corresponding to the processing unit;
- an acceleration determining circuit configured to:
- based on an obtained logical to physical mapping table, determine whether address values of a plurality of target physical addresses in the obtained logical to physical mapping table corresponding to a plurality of target logical addresses are continuous;
- wherein the processing unit is configured to:
- obtain, from the acceleration determining circuit, a first instruction indicating that the address values of the plurality of target physical addresses are determined to be continuous;
- based on the first instruction, select one of the plurality of target physical addresses as a base physical address, and set a base physical address offset based on address values of remaining target physical addresses;
- and
- store the base physical address and the base physical address offset into the cache, as a mapping relationship of the plurality of target logical addresses corresponding to the plurality of target physical addresses.
Dependencies are inferred from the claim text.