Clock generator device and clock generation method
AssigneeSigmastar Technology Ltd.
InventorWei-Ping Wang
Life of this patent
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Abstract
A clock generator device includes a first clock generator circuit, a second clock generator circuit, a detector circuit and a selection circuit. The first clock generator circuit has a first starting voltage and generates a first clock signal in response to a supply voltage. The second clock generator circuit has a second starting voltage and generates a second clock signal in response to the supply voltage. The detector circuit detects the second clock signal to generate a validation signal. The selection circuit selectively outputs one of the first clock signal and the second clock signal according to the validation signal. The first starting voltage is lower than the second starting voltage.
Claims8
A clock generator device, comprising:
- a first clock generator circuit, having a first starting voltage, generating a first clock signal in response to a supply voltage;
- a second clock generator circuit, having a second starting voltage, generating a second clock signal in response to the supply voltage, wherein the first starting voltage is lower than the second starting voltage;
- a first detector circuit, detecting the second clock signal to generate a validation signal;
- a selection circuit, selectively outputting one of the first clock signal and the second clock signal according to the validation signal;
- a second detector circuit, detecting the first clock signal to generate a first control signal;
- a first delay circuit, for delaying the validation signal to generate a first signal;
- a second delay circuit, for delaying the first control signal to generate a second signal;
- and
- a logic gate circuit, for generating a second control signal according to the first signal and the second signal;
- wherein, a delay time of the first delay circuit is less than a delay time of the second delay circuit.
A clock generation method, comprising:
- generating a first clock signal by a first clock generator circuit in response to a supply voltage, the first clock generator circuit having a first starting voltage;
- generating a second clock signal by a second clock generator circuit in response to the supply voltage, the second clock generator circuit having a second starting voltage, wherein the first starting voltage is lower than the second starting voltage;
- detecting the second clock signal to generate a validation signal;
- and
- selectively outputting one of the first clock signal and the second clock signal according to the validation signal;
- detecting the first clock signal by a second detector circuit to generate a first control signal;
- delaying the validation signal by a first delay circuit to generate a first signal;
- delaying the first control signal by a second delay circuit to generate a second signal;
- and
- generating a second control signal by a logic gate circuit according to the first signal and the second signal;
- wherein, a delay time of the first delay circuit is less than a delay time of the second delay circuit.
Dependencies are inferred from the claim text.