Debug and trace circuit in lockstep architectures, associated method, processing system, and apparatus

A method comprising:

• transitioning from a functional mode of a processing system to a debug mode of the processing system after a debugger is coupled to the processing system, the processing system comprising a main and shadow processing cores operating in lockstep;
• and
• during functional mode:
• receiving functional inputs with a main functional core of the main processing system and with a shadow functional core of the shadow processing system,
• processing the functional inputs in parallel with the main and shadow functional cores in synchrony with a core clock,
• receiving debug data from the debugger in synchrony with a debug clock, the debug clock being asynchronous with the core clock,
• synchronizing the debug data to the core clock and providing the synchronized debug data to a debug bus in synchrony with the core clock,
• receiving the synchronized debug data from the debug bus with a main debug circuit of the main processing core and with a shadow debug circuit of the shadow processing core,
• comparing outputs from the main and shadow functional cores and asserting an alarm signal when a discrepancy between the outputs from the main and shadow functional cores is detected, and
• reacting to the assertion of the alarm signal.

A vehicle comprising:

• a debug port;
• an electronic control unit (ECU);
• and
• a processing system comprising:
• a main processing core comprising a main functional core and a main debug circuit, the main debug circuit having a debug input coupled to a debug bus and a debug output coupled to the debug bus,
• a shadow processing core comprising a shadow functional core and a shadow debug circuit, the shadow debug circuit having a debug input coupled to the debug bus, wherein the main and shadow processing cores are configured to operate in lockstep based on a core clock;
• a redundancy checker circuit configured to receive first outputs from the main and shadow functional cores and assert an alarm signal at an output terminal when a discrepancy between the first outputs from the main and shadow functional cores is detected, the output terminal of the redundancy checker circuit being coupled to the ECU;
• and
• a debug bus synchronizer circuit having a debug input coupled to the debug port and configured to receive input debug data in synchrony with a debug clock from the debug port, and an output coupled to the debug bus, wherein the debug bus synchronizer circuit is configured to provide synchronized debug data in synchrony with the core clock to the debug bus based on the input debug data, wherein the main and shadow debug circuits are configured to receive the synchronized debug data in synchrony with the core clock from the debug bus, and wherein the debug clock is asynchronous with respect to the core clock.