# US 11,892,503 B2 · Semiconductor device and test method of semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,892,503 B2 - Document ID: US11892503B2 - Status: Granted - Kind: B2 - Application number: 17/898,102 - Filed: 2022-08-29 - Published: 2023-09-21 - Granted: 2024-02-06 - Earliest claimed: 2022-03-17 - Assignees: Toshiba Tec Kabushiki Kaisha - Applicants: Kioxia Corporation - Inventors: Takuya Kusaka; Hirosuke Narai; Kazunori Masuda; Makoto Iwai - Web page: https://patentgrep.com/patent/US11892503B2 ## CPC - G01R 31/2896: {Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00)} - G01R 31/2853: {Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66)} - G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)} - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 90/00: Package configurations - H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads} - H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/284: {characterised by structural arrangements for measuring or testing} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes first and second chips in a package. A first pad is on the first chip and electrically connected to a node between a power supply pad and a ground pad on the first chip. Second and third pads are on the second chip. An internal wiring connects the first pad to the second pad within the package. A power circuit on the semiconductor chip configured to supply a current to the second pad. A switch is on the second chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power circuit. A control circuit is on the second chip and configured to output a first signal for the switch in response to a test signal supplied to the third pad and a second signal to the power circuit to cause the power circuit to output current. ## Claims ### Claim 1 A semiconductor device, comprising: a first semiconductor chip in a package; a second semiconductor chip in the package; a first pad on the first semiconductor chip and electrically connected to a node between a power supply pad and a ground pad on the first semiconductor chip; a second pad on the second semiconductor chip; a third pad on the second semiconductor chip; an internal wiring connecting the first pad to the second pad within the package; a power supply circuit on the second semiconductor chip configured to supply a current to the second pad; a switch on the second semiconductor chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power supply circuit; and a control circuit on the second semiconductor chip configured to output: a first control signal for controlling ON and OFF states of the switch in response to a test signal supplied to the third pad, and a second control signal to the power supply circuit to cause the power supply circuit to output current. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising: a first external terminal on an outside of the package, the first external terminal being electrically connected to the third pad. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the first external terminal is electrically connected to the third pad via another internal wiring connected to a pad on the first semiconductor chip. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, further comprising: a wiring substrate on which the first and second semiconductor chips are mounted, wherein the first external terminal is electrically connected to the third pad via an interconnection in the wiring substrate. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein third pad is connected to the interconnection by a bonding wire extending from the third pad to a pad on the wiring substrate electrically connected to the interconnection. ### Claim 6 (depends on 4) The semiconductor device according to claim 4, wherein the internal wiring is another interconnection in the wiring substrate. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the test signal is generated and supplied by an external tester connected to an external terminal of the package. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the first semiconductor chip includes an internal circuit configured to generate and supply the test signal in response to an external signal supplied to an external terminal of the package. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the first semiconductor chip is a controller chip, and the second semiconductor chip is a memory chip. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the first semiconductor chip includes a plurality of the first pads, the second semiconductor chip includes a plurality of the second pads corresponding to the first pads, respectively, a plurality of internal wirings respectively connecting the first pads and the second pads, and a plurality of the switches respectively between the second pads and the power supply circuit, and the control circuit is further configured to output first control signals for controlling ON and OFF states of each of the switches in sequence. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are connected to the internal wiring at internal wiring ends most distant from each other. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the internal wiring is a bonding wire connecting the first pad and the second pad. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the first pad and the second pad are directly connected to a wiring substrate, and the internal wiring is in the wiring substrate. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, further comprising: a first protective diode between the node and the power supply pad; and a second protective diode between the node and ground pad. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein the second pad is electrically connected to an internal circuit of the second semiconductor chip along a path not passing through the switch. ### Claim 16 A packaged semiconductor device, comprising: a wiring substrate; a first semiconductor chip on the wiring substrate; a second semiconductor chip on the wiring substrate; a first pad on the first semiconductor chip and electrically connected to a node between a power supply pad and a ground pad on the first semiconductor chip; a second pad on the second semiconductor chip; a third pad on the second semiconductor chip; an internal wiring connecting the first pad to the second pad; a power supply circuit on the second semiconductor chip configured to supply a current to the second pad; a switch on the second semiconductor chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power supply circuit; a control circuit on the second semiconductor chip configured to output: a first control signal for controlling ON and OFF states of the switch in response to a test signal supplied to the third pad, and a second control signal to the power supply circuit to cause the power supply circuit to output current; and a sealing resin covering the first and second semiconductor chips, the internal wiring, and a first surface of the wiring substrate. ### Claim 17 (depends on 16) The packaged semiconductor device according to claim 16, wherein the internal wiring comprises a bonding wire. ### Claim 18 (depends on 16) The packaged semiconductor device according to claim 16, wherein the third pad is electrically connected to an external terminal on a second surface of the wiring substrate on an opposite side of the wiring substrate from the first surface via a bonding wire connecting to the third pad to a pad terminal on the first surface of the wiring substrate. ### Claim 19 A test method for a packaged semiconductor device including an internal wiring connecting a first pad on a first semiconductor chip to a second pad on a second semiconductor chip, the test method comprising: receiving a test signal at a third pad on the second semiconductor chip, the third pad being electrically connected to a control circuit on the second semiconductor chip; outputting a first control signal from the control circuit to a power supply circuit on the second semiconductor chip in response to the receiving of the test signal at the third pad, the first control signal causing the power supply circuit to output a current to a wiring connected to the second pad; outputting a second control signal from the control circuit to a switch in response to the receiving of the test signal at the third pad, the switch being on the wiring connecting the second pad and the power supply circuit and controlling whether current from the power supply circuit reaches the internal wiring via the second pad; measuring a voltage between a power supply pad and a ground pad, the first pad being electrically connected to a node between the power supply pad and the ground pad; and detecting a connection state of the internal wiring based on the measuring of the voltage. ### Claim 20 (depends on 19) The test method according to claim 19, wherein the packaged semiconductor device is a multi-chip memory device.