Diagnosing multicycle transition faults and/or defects with AT-speed ATPG test patterns

A system comprising:

• automatic test equipment (ATE) that applies N-cycle at-speed test patterns to a fabricated integrated circuit (IC) chip that is based on an IC design and provides test result data characterizing application of the N-cycle at-speed test patterns to the fabricated IC chip, where N is an integer greater than or equal to two, in which the test result data includes a set of miscompare values characterizing a difference between an expected result and a result measured by the ATE for a given N-cycle at-speed test pattern of the N-cycle at-speed test patterns;
• a non-transitory memory that stores machine-readable instructions;
• and
• a processing unit that accesses the memory and executes the machine-readable instructions, the machine-readable instructions comprising:
• an IC test engine that generates the N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of the IC design;
• and
• a diagnostics engine that:
• employs a fault simulator to fault-simulate a subset of the N-cycle at-speed test patterns against a fault model that includes multicycle transition faults and/or defects utilizing sim-shifting to diagnose a second set of transition faults and/or defects in the fabricated IC chip that are only detectable with a multicycle test pattern having one or more additional initialization cycles than a corresponding one of the N-cycle at-speed test patterns;
• and
• scores candidate faults and/or defects in the first set of transition faults and/or defects and the second set of transition faults and/or defects for applicable test patterns of the subset of the N-cycle at-speed test patterns to determine a most likely fault and/or defect present in the fabricated IC chip.

A method for diagnosing faults and/or defects in a fabricated integrated circuit (IC) chip, the method comprising:

• generating, by an IC test engine operating on a computing platform, N-cycle at-speed test patterns for testing for candidate faults and/or defects of a first set of transition faults and/or defects of an IC design, where N is an integer greater than or equal to two;
• applying, by automatic test equipment (ATE) the N-cycle at-speed test patterns to a fabricated IC chip that is based on the IC design and provides test result data characterizing application of the N-cycle at-speed test patterns to the fabricated IC chip, in which the test result data includes a set of miscompare values characterizing a difference between an expected result and a result measured by the ATE for a given N-cycle at-speed test pattern of the N-cycle at-speed test patterns;
• selectively fault-simulating, by a fault simulator of a diagnostics engine operating on the computing platform, a subset of the N-cycle at-speed test patterns against a fault model that includes multicycle transition faults and/or defects utilizing sim-shifting to diagnose a second set of transition faults and/or defects in the fabricated IC chip that are only detectable with multicycle test patterns having one or more additional initialization cycles than a corresponding one of the N-cycle at-speed test patterns;
• and
• scoring, by the diagnostics engine candidate, faults and/or defects in the first set of transition faults and/or defects and the second set of transition faults and/or defects for applicable test patterns of the subset of the N-cycle at-speed test patterns to determine a most likely fault and/or defect present in the fabricated IC chip.