Interconnect landing method for RRAM technology

An integrated chip, comprising:

• a first interconnect within a first inter-level dielectric (ILD) layer over a substrate;
• a memory device disposed over the first interconnect and surrounded by a second ILD layer;
• a second interconnect extending from a top of the second ILD layer to an upper surface of the memory device, wherein the second interconnect comprises a conductive core and a barrier layer, the barrier layer having a horizontally extending surface contacting the conductive core along an interface that is vertically below the upper surface of the memory device;
• and
• sidewall spacers arranged along opposing sides of the memory device, each of the sidewall spacers having a top rectangular portion between and the barrier layer and the memory device and having a vertical side surface in direct contact with the barrier layer.

An integrated chip, comprising:

• a first interconnect within a first inter-level dielectric (ILD) layer over a substrate;
• a memory device disposed over the first interconnect and surrounded by a second ILD layer;
• sidewall spacers arranged along opposing sides of the memory device;
• an etch stop layer arranged on the sidewall spacers, wherein the sidewall spacers have a different height than the etch stop layer;
• and
• a second interconnect extending from a top of the second ILD layer to an upper surface of the memory device and to upper surfaces of the sidewall spacers leveled with the upper surface of the memory device, wherein the second interconnect has a bottommost surface continuously extending from directly over an upper surface of one of the sidewall spacers to laterally past a sidewall of the etch stop layer, the bottommost surface contacting the one of the sidewall spacers along an interface that is below the upper surface of the memory device.