Magnetic junction memory device and reading method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsChan Kyung Kim, Eun Ji Lee, Ji Yean Kim, Tae Seong Kim, Jae Wook Joo
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Abstract
A magnetic junction memory device is provided. The magnetic junction memory device including a sensing circuit including a sensing node, the sensing node being connected to a first end of a transistor and configured to change a voltage of the sensing node in accordance with a resistance of a magnetic junction memory cell, a gating voltage generator circuit configured to generate a gating voltage of the transistor using a reference resistor and a reference voltage, and a read circuit configured to read data from the magnetic junction memory cell using the reference voltage and the voltage of the sensing node.
Claims20
A magnetic junction memory device comprising:
- a first single-transistor common-gate amplifier circuit including a first transistor which is gated by a gating voltage and has a first end connected to a first sensing node, the first single-transistor common-gate amplifier circuit configured to determine a voltage of the first sensing node by applying a first read current to a first reference resistor;
- a second single-transistor common-gate amplifier circuit including a second transistor which is gated by the gating voltage and has a first end connected to a second sensing node, the second single-transistor common-gate amplifier circuit configured to determine a voltage of the second sensing node by applying a second read current to a second reference resistor, which has a different resistance from the first reference resistor;
- and
- a third single-transistor common-gate amplifier circuit including a third transistor which is gated by the gating voltage and has a first end connected to a third sensing node, the third single-transistor common-gate amplifier circuit configured to determine a voltage of the third sensing node by applying a third read current to a magnetic junction memory cell.
A magnetic junction memory device comprising:
- a first single-transistor common-gate amplifier circuit including a first transistor which is gated by a gating voltage and connected to a first sensing node, the first single-transistor common-gate amplifier circuit configured to determine a voltage of the first sensing node by applying a first read current to a magnetic junction memory cell;
- a gating voltage generator circuit configured to generate the gating voltage of the first transistor using a reference resistor and a reference voltage;
- a precharge circuit configured to precharge voltages of first and second output nodes to the reference voltage;
- and
- a latch configured to
- develop the voltages of the first and second output nodes in accordance with the voltage of the first sensing node, and
- latch data stored in the magnetic junction memory cell based on the developed voltages of the first and second output nodes.
A read method of a magnetic junction memory device including a sensing circuit which receives a gating voltage generated by using first and second reference resistors, and reads data from a magnetic junction memory cell using a reference voltage and a voltage of a sensing node that changes in accordance with a resistance of the magnetic junction memory cell, the read method comprising:
- during a first period, developing a voltage of a first output node in accordance with the voltage of the sensing node and maintaining a voltage of a second output node at the reference voltage;
- and
- during a second period, which follows the first period, developing the voltages of the first and second output nodes in accordance with the voltage of the sensing node.
Dependencies are inferred from the claim text.