Semiconductor device including dummy channels and through wiring structure

A semiconductor device, comprising:

• a peripheral circuit region including a first substrate and circuit devices on the first substrate;
• a memory cell region including a second substrate on the first substrate, a horizontal conductive layer on the second substrate, gate electrodes stacked on the horizontal conductive layer in a first direction perpendicular to an upper surface of the second substrate and spaced apart from each other, and channel structures extending in the gate electrodes in the first direction, each of the channel structures including a channel layer in physical contact with the horizontal conductive layer;
• and
• a through wiring region including a through contact plug extending in the first direction and electrically connecting the memory cell region to the peripheral circuit region, an insulating region bordering the through contact plug, and dummy channel structures partially extending into the insulating region, in the first direction, each of the dummy channel structures including the channel layer and being spaced apart from the horizontal conductive layer in the first direction,
• wherein each of the channel structures has a first height in the first direction, and each of the dummy channel structures has a second height smaller than the first height.

A semiconductor device, comprising:

• a substrate;
• gate electrodes stacked on the substrate and spaced apart from each other;
• channel structures extending in the gate electrodes in a first direction perpendicular to an upper surface of the substrate, each of the channel structures including a channel layer;
• an insulating region side by side with the gate electrodes in a second direction perpendicular to the first direction;
• and
• dummy channel structures extending into the insulating region in the first direction, each of the dummy channel structures including the channel layer,
• wherein each of the dummy channel structures has a first region in an upper portion of the insulating region along the first direction and includes the channel layer, and a second region, which includes a lower end along the first direction and does not include the channel layer,
• wherein the lower end of each of the dummy channel structures is at a level higher than a level of a lower end of each of the channel structures in the first direction with the substrate providing a base reference level.