Device, a method used in forming a circuit structure, a method used in forming an array of elevationally-extending transistors and a circuit structure adjacent thereto

A device comprising:

• an array of elevationally-extending transistors;
• and
• a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array, the circuit structure comprising:
• a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material, one of the conductive steps comprising conductive material that extends into the array and which electrically couples to some of the transistors in the array, another of the conductive steps comprising conductive material that does not extend into the array and which does not electrically couple to any transistor in the array;
• operative conductive vias individually extending elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and which individually electrically couple to an electronic component below the vertically-alternating tiers;
• and
• dummy structures individually extending elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers.

A device comprising:

• an array of elevationally-extending transistors;
• and
• a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array, the circuit structure comprising:
• a first stair step structure and an adjacent second stair step structure individually comprising vertically-alternating tiers comprising first and second opposing sets of conductive steps, the conductive steps being at least partially elevationally separated from one another by insulative material in each of the first and second stair step structures;
• an elevationally-outer landing between the first stair step structure and the second stair step structure;
• operative conductive vias in each of the first and second stair step structures, the operative conductive vias individually extending elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers of the respective first or second stair step structure and which individually electrically couple to an electronic component below the vertically-alternating tiers of the respective first or second stair step structure;
• first dummy structures in each of the first and second stair step structures, the first dummy structures individually extending elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers of the respective first or second stair step structure;
• and
• a second dummy structure extending elevationally through the landing.

A device comprising:

• an array of elevationally-extending transistors;
• and
• a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array, the circuit structure comprising:
• a stair step structure comprising vertically-alternating tiers comprising first and second opposing flights of conductive steps, the conductive steps being at least partially elevationally separated from one another by insulative material;
• operative conductive vias individually extending elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and which individually electrically couple to an electronic component below the vertically-alternating tiers, the operative conductive vias extending elevationally only through the steps in one of the first or second flights and not in the other of the first and second flights;
• first-flight-dummy structures individually extending elevationally through one of the first-flight conductive steps at least to the bottom of the vertically-alternating tiers;
• and
• second-flight-dummy structures individually extending elevationally through one of the second-flight conductive steps at least to the bottom of the vertically-alternating tiers.

A device comprising:

• an array of elevationally-extending transistors comprising memory cells;
• and
• a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array, the circuit structure comprising:
• a first stair step structure and an adjacent second stair step structure individually comprising vertically-alternating tiers comprising first and second opposing flights of conductive steps, the conductive steps being at least partially elevationally separated from one another by insulative material in each of the first and second stair step structures;
• operative conductive vias in each of the first and second stair step structures, the operative conductive vias individually extending elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers of the respective first or second stair step structure and which individually electrically couple to an electronic component below the vertically-alternating tiers of the respective first or second stair step structure;
• first-flight-dummy structures in each of the first and second stair step structures, the first-flight-dummy structures individually extending elevationally through one of the first-flight conductive steps in the respective first or second stair step structure at least to the bottom of the vertically-alternating tiers of the respective first or second stair step structure;
• and
• second-flight-dummy structures in each of the first and second stair step structures, the second-flight-dummy structures individually extending elevationally through one of the second-flight conductive steps in the respective first or second stair step structure at least to the bottom of the vertically-alternating tiers of the respective first or second stair step structure.