Back to results
US 11,889,692 B2Granted
Vertical memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsChang-Min Choi, Ju-Young Lim, Su-Jin Ahn
Life of this patent
Estimating the term…
Abstract
A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.
Claims20
A vertical memory device, comprising:
- a substrate;
- a plurality of channels extending in a vertical direction with respect to a top surface of the substrate;
- a plurality of gate lines surrounding a predetermined number of channels from among the channels, wherein the gate lines are arranged and spaced apart from one another along the vertical direction, and the gate lines comprise a ground selection line (GSL), a plurality of word lines, and a string selection line (SSL) sequentially stacked on the top surface of the substrate;
- a plurality of common wirings electrically connected to the gate lines, wherein a first one of the common wirings is electrically connected to the SSL, a second one of the common wirings is electrically connected to the GSL, and remaining ones of the common wirings other than the first and second common wirings are electrically connected to the word lines,
- wherein the first one of the common wirings, the second one of the common wirings, and the remaining ones of the common wirings are disposed at a same level and are respectively connected to the SSL, the GSL, and the word lines via a plurality of contacts,
- wherein the gate lines extend in a first direction, and the common wirings extend in a second direction crossing the first direction,
- wherein a length of the first one of the common wirings, a length of the second one of the common wirings, and lengths of the remaining ones of the common wirings are about equal to each other in the second direction;
- and
- a plurality of signal wirings electrically connected to the gate lines via the common wirings, wherein the signal wirings are distributed at a plurality of levels.
6 more elements
A vertical memory device, comprising:
- a substrate;
- a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate;
- a plurality of gate lines arranged and spaced apart from one another along the first direction, wherein the plurality of gate lines surround the channels;
- a plurality of common wirings electrically connected to the gate lines;
- a plurality of first contacts extending in the first direction, wherein a first end of each first contact is connected to a corresponding common wiring from among the common wirings, and a second end of each first contact is connected to a corresponding gate line from among the gate lines,
- wherein the second ends of the first contacts are disposed at different levels from one another,
- wherein an uppermost gate line from among the gate lines is connected to a corresponding common wiring via a corresponding first contact;
- a plurality of first signal wirings electrically connected to lower gate lines from among the gate lines via the common wirings;
- and
- a plurality of second signal wirings electrically connected to upper gate lines from among the gate lines via the common wirings,
- wherein the second signal wirings are disposed higher than the first signal wirings in the first direction, the first signal wirings are electrically connected to adjacent common wirings from among the common wirings, and the second signal wirings are electrically connected to adjacent common wirings from among the common wirings,
- wherein, in a plan view, the first signal wirings are not disposed between the second signal wirings, and the second signal wirings are not disposed between the first signal wirings.
9 more elements
A vertical memory device, comprising:
- a substrate;
- a plurality of channels extending lengthwise in a first direction substantially vertical to a top surface of the substrate;
- a plurality of gate lines arranged and spaced apart from one another along the first direction, each of the plurality of gate lines extending lengthwise in a second direction, and the plurality of gate lines surrounding the channels;
- a plurality of common wirings electrically connected to the gate lines, each of the plurality of common wirings extending lengthwise in a third direction crossing the second direction;
- a plurality of first contacts extending lengthwise in the first direction, wherein a first end of each first contact is connected to a corresponding common wiring from among the common wirings, and a second end of each first contact is connected to a corresponding gate line from among the gate lines,
- wherein the second ends of the first contacts disposed at different levels from one another,
- wherein an uppermost gate line from among the gate lines is connected to a corresponding common wiring from among the common wirings via a corresponding first contact from among the first contacts;
- a plurality of first signal wirings electrically connected to lower gate lines from among the gate lines via the common wirings;
- and
- a plurality of second signal wirings electrically connected to upper gate lines from among the gate lines via the common wirings,
- wherein the second signal wirings are disposed higher than the first signal wirings in the first direction,
- wherein the first signal wirings are electrically connected to adjacent first common wirings from among the common wirings, the adjacent first common wirings being disposed in the second direction, and
- wherein the second signal wirings are electrically connected to adjacent second common wirings from among the common wirings, the adjacent second common wirings being disposed in the second direction.
10 more elements
Dependencies are inferred from the claim text.