Dual port memory cell with improved access resistance
AssigneeSTMicroelectronics International N.V.
InventorsTushar Sharma, Tanmoy Roy, Shishir Kumar
Life of this patent
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Abstract
The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.
Claims19
A method, comprising:
- forming a dual port bit memory cell, by:
- forming a first active region in a semiconductor layer, the forming the first active region including:
- forming a first gate that selectively couples a first bit line node to a first memory cell node;
- forming a second gate that selectively couples the first memory cell node to a first power line node;
- forming a third gate that selectively couples the first power line node to a second memory cell node;
- and
- forming a fourth gate that selectively couples the second memory cell node to the first inverted bit line node.
A method, comprising:
- reading a memory cell by:
- setting a first bit line and a first inverted bit line to a first power node, the first bit line coupled to a first memory cell node, the first inverted bit line coupled to a second memory cell node, the first memory cell node and the second memory cell node being coupled together;
- disconnecting the first bit line and the first inverted bit line from the first power node;
- activating a first transistor coupled to the first bit line and activating a second transistor coupled to the first inverted bit line by activating a first word line coupled to gate of the first and second transistors;
- in response to the first memory cell node having a high value and the second memory cell node having a low value, discharging a third transistor to the first inverted bit line;
- in response to the first memory cell node having a low value and the second memory cell node having a high value, discharging a fourth transistor to the first bit line.
A method, comprising:
- forming in a substrate, a first active area and a second active area spaced away from one another, forming the first active area including:
- forming a first bit line node;
- forming a first memory cell node;
- forming a first power line node;
- forming a second memory cell node;
- and
- forming a first inverted bit line node;
- forming the second active area including:
- forming a third memory cell node;
- and
- forming a fourth memory cell node;
- and
- forming a first metallization level over the substrate, including:
- forming a first routing line coupling the first memory cell node to the third memory cell node;
- and
- forming a second routing line coupling the second memory cell node to the fourth memory cell node.
Dependencies are inferred from the claim text.