Dual port SRAM cell and design method thereof

An integrated circuit comprising:

• a first bit cell and a second bit cell adjacent to the first bit cell in a first direction;
• a boundary dummy line extending in a second direction perpendicular to the first direction at a boundary between the first bit cell and the second bit cell and electrically independent from the first bit cell and the second bit cell;
• a first bit line pair connected to the first bit cell, the first bit line pair including a first bit line and a second bit line extending in the second direction and spaced apart from each other in the first direction;
• a first complementary bit line pair spaced apart from the first bit line pair in the first direction and connected to the first bit cell, the first complementary bit line pair including a first complementary bit line complementary to the first bit line and a second complementary bit line complementary to the second bit line;
• a power line group including a plurality of power lines provided between the first bit line pair and the first complementary bit line pair and spaced apart from the first bit line pair in the first direction, the power line group being configured to apply a voltage to the first bit cell;
• a first word line provided between the first bit line and the second bit line and connected to the first bit cell;
• and
• a second word line provided between the first complementary bit line and the second complementary bit line and connected to the first bit cell.

An integrated circuit design method comprising:

• forming a first bit cell;
• forming, on the first bit cell, a first bit line pair including a first bit line and a second bit line spaced apart from each other in a first direction and extending in a second direction perpendicular to the first direction;
• forming, on the first bit cell, a first complementary bit line pair including a first complementary bit line and a second complementary bit line spaced apart from each other in the first direction and extending in the second direction;
• and
• forming, on the first bit cell, a first word line between the first bit line and the second bit line and a second word line between the first complementary bit line and the second complementary bit line.