Equalizer, operating method of equalizer and system including equalizer

An operating method of an equalizer, the operating method comprising:

• amplifying an input signal through an input amplifier;
• generating 1-1 to 1-N feedback signals through a first sampling circuit, wherein N is a natural number greater than or equal to 2;
• generating 2-1 to 2-M feedback signals through a second sampling circuit, wherein M is a natural number greater than or equal to 2;
• performing, through a first arithmetic circuit, weighted summation of received feedback signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals;
• performing, through a third arithmetic circuit, weighted summation of received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals;
• performing, through a second arithmetic circuit, weighted summation of an output signal of the input amplifier, an output signal of the first arithmetic circuit, and the 2-1 feedback signal, and outputting the weighted-summed output signal of the input amplifier, output signal of the first arithmetic circuit, and 2-1 feedback signal to the first sampling circuit;
• and
• performing, through a fourth arithmetic circuit, weighted summation of the output signal of the input amplifier, an output signal of the third arithmetic circuit, and the 1-1 feedback signal and outputting the weighted-summed output signal of the input amplifier, output signal of the third arithmetic circuit, and 1-1 feedback signal to the second sampling circuit.

A system comprising:

• a host device;
• a memory device configured to operate based on a request received from the host device;
• and
• an interface including an equalizer, the interface being configured to provide communication between the host device and the memory device,
• wherein the equalizer comprises:
• an input amplifier configured to amplify and output an input signal;
• a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2;
• and
• a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2,
• wherein the first arithmetic circuit is configured to perform weighted summation of received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals and outputs the weighted-summed received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals,
• the second arithmetic circuit is configured to perform weighted summation of an output signal of the input amplifier, an output signal of the first arithmetic circuit, and the 2-1 feedback signal and outputs the weighted-summed output signal of the input amplifier, output signal of the first arithmetic circuit, and 2-1 feedback signal to the first sampling circuit,
• the third arithmetic circuit is configured to perform weighted summation of received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals and outputs the weighted-summed received feedbacks signals among the 1-2 to 1-N feedback signals and the 2-2 to 2-M feedback signals, and
• the fourth arithmetic circuit is configured to perform weighted summation of the output signal of the input amplifier, an output signal of the third arithmetic circuit, and the 1-1 feedback signal and outputs the weighted-summed output signal of the input amplifier, output signal of the third arithmetic circuit, and 1-1 feedback signal to the second sampling circuit.