Elimination of probability of bit errors in successive approximation register (SAR) analog-to-digital converter (ADC) logic

A successive approximation registers (SAR) analog-to-digital converter (ADC) comprising:

• a digital-to-analog converter (DAC) to generate a first DAC output voltage based on a digital output code associated with an analog input voltage;
• a comparator to compare the first DAC output voltage to the analog input voltage to generate a comparison result including a first positive output and first negative output;
• and
• SAR logic circuitry comprising:
• first logic circuitry to gate, based at least in part on a digital feedback, at least one of the first positive output or the first negative output of the comparator to second logic circuitry, the digital feedback comprising information associated with at least one of an opposite polarity of the a first positive output or an opposite polarity of the first negative output;
• and
• the second logic circuitry downstream of the first logic circuitry;
• wherein the digital feedback comprises an output of the second logic circuitry, the output responsive to at least one of a second positive output or a second negative output of the comparator;
• and
• wherein:
• the first positive output and the first negative output of the comparator are associated with a current bit trial;
• and
• the at least one of the second positive output or the second negative output of the comparator are associated with a previous bit trial.

A successive approximation registers (SAR) analog-to-digital converter (ADC) comprising:

• an analog input to receive an analog input voltage;
• sample-and-hold circuitry coupled to the analog input;
• a digital-to-analog converter (DAC);
• a comparator coupled to an output of the sample-and-hold circuitry and an output of the DAC;
• and
• SAR logic circuitry comprising:
• a shift register;
• a first digital path comprising:
• first detection circuitry to receive one of a first positive output or a first negative output of the comparator, an output of the shift register, and a first digital feedback associated with a second digital path;
• and
• latching circuitry coupled to an output of the first detection circuitry;
• the second digital path comprising:
• second detection circuitry to receive the other one of the first positive output or the first negative output of the comparator, the output of the shift register, and a second digital feedback associated with the first digital path, wherein the second digital feedback corresponds to an output downstream of the latching circuitry;
• and
• wherein:
• the first positive output and the first negative output of the comparator are associated with a current bit trial;
• and
• at least one of a second positive output or a second negative output of the comparator are associated with a previous bit trial.