Successive approximation register analog-to-digital converter with embedded filtering

An analog-to-digital converter (ADC) comprising:

• a comparator having an input and an output;
• a control circuit comprising:
• a digital sample register having an input and an output;
• a successive approximation register (SAR) having an input coupled to the output of the comparator, having a first output coupled to the input of the digital sample register, and having a second output;
• and
• a selector circuit having a first input coupled to the output of the digital sample register, having a second input coupled to the second output of the SAR, and having a switch control output, wherein the control circuit is configured to provide switch control signals at the switch control output;
• and
• a switched capacitor circuit having a switch control input coupled to the switch control output, having an output coupled to the input of the comparator, and the switched capacitor circuit comprising capacitors coupled to switches, and configured to, in a sample acquisition cycle and responsive to the switch control signals:
• sample an analog input signal using a first subset of the capacitors;
• and
• charge a second subset of the capacitors based on a digital sample value provided by the ADC prior to the sample acquisition cycle, wherein the selector circuit is configured to:
• route the output of the digital sample register to the switched capacitor circuit during the sample acquisition cycle;
• and
• route the second output of the SAR to the switched capacitor circuit during sample digitization.

An analog-to-digital converter (ADC) comprising:

• a switched capacitor circuit having a switch control input and an output, and comprising switches coupled to the switch control input and coupled to capacitors;
• a comparator having an input coupled to the output of the switched capacitor circuit and having an output;
• and
• a control circuit comprising:
• a digital sample register having an input and an output;
• a successive approximation register (SAR) having an input coupled to the output of the comparator, having a first output coupled to the input of the digital sample register, and having a second output;
• and
• a selector circuit having a first input coupled to the output of the digital sample register, having a second input coupled to the second output of the SAR, and a switch control output coupled to the switch control input, wherein the selector circuit is configured to:
• route the output of the digital sample register to the switched capacitor circuit during a sample acquisition cycle;
• and
• route the second output of the SAR to the switched capacitor circuit during sample digitization.

A receiver comprising:

• a mixer circuit configured to down convert a received radio frequency signal and provide a down-converted analog signal;
• and
• an analog-to-digital converter (ADC) coupled to the mixer circuit and configured to digitize the down-converted analog signal, the ADC comprising:
• a switched capacitor circuit comprising switches coupled to capacitors;
• a comparator coupled to the switched capacitor circuit;
• and
• a control circuit coupled to the switched capacitor circuit and to the comparator, the control circuit comprising:
• a digital sample register having an input and an output;
• a successive approximation register (SAR) having an input coupled to the output of the comparator, having a first output coupled to the input of the digital sample register, and having a second output;
• and
• a selector circuit having a first input coupled to the output of the digital sample register, and a second input coupled to the second output of the SAR, wherein the selector circuit is configured to:
• route the output of the digital sample register to the switched capacitor circuit during a sample acquisition cycle;
• and
• route the second output of the SAR to the switched capacitor circuit during sample digitization.