Semiconductor integrated circuit and receiver device
AssigneeKioxia Corporation
InventorFumihiko Tachibana
Life of this patent
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Abstract
A semiconductor integrated circuit according to an embodiment includes an A/D converter, first and second equalizer circuits, and first and second controllers. The first equalizer circuit includes a first tap. The first and second equalizer circuits receive a signal based on a digital signal, and output first and second signals, respectively. The first controller adjusts a phase of a clock signal based on the first signal. The second controller an operation of adjusting a control parameter including a tap coefficient. In the operation, the second controller adjusts a tap coefficient of each of taps of the second equalizer circuit, and adjusts a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.
Claims20
A semiconductor integrated circuit comprising:
- an A/D converter configured to convert an analog signal into a digital signal based on a clock signal;
- a first equalizer circuit includes a plurality of taps including a first tap that is one tap after a center tap, the first equalizer circuit receiving a signal based on the digital signal and outputting a first signal;
- a first data comparator circuit configured to determine data based on the first signal and output the determined data as first data;
- a second equalizer circuit includes a plurality of taps, the second equalizer circuit receiving a signal based on the digital signal and outputting a second signal;
- a second data comparator circuit configured to determine data based on the second signal and output the determined data to an outside;
- a first control circuit configured to adjust a phase of the clock signal based on the first signal and the first data, and input the adjusted clock signal to the A/D converter;
- and
- a second control circuit configured to control each of the first equalizer circuit and the second equalizer circuit, and execute an operation of adjusting a control parameter including a tap coefficient, wherein
- in the operation, the second control circuit is configured to adjust a tap coefficient of each of the taps of the second equalizer circuit, and adjust a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.
A semiconductor integrated circuit comprising:
- an A/D converter configured to convert an analog signal into a digital signal based on a clock signal;
- a first equalizer circuit configured to receive a signal based on the digital signal and output a first signal;
- a second equalizer circuit configured to receive a signal based on the digital signal and output a second signal;
- a first data comparator circuit configured to determine data based on the first signal and output the determined data as first data;
- a control circuit configured to adjust a phase of the clock signal based on the first signal and the first data by executing an adjusting operation, and input the adjusted clock signal to the A/D converter;
- and
- a second data comparator circuit configured to determine data based on the second signal and output the determined data to an outside, wherein
- in the adjusting operation, the control circuit is configured to perform adjustment to make a gain of the first signal decrease.
Dependencies are inferred from the claim text.