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US 11,888,495 B2Granted
Analog multiplexer circuit and analog-digital conversion system
AssigneeNippon Telegraph and Telephone Corporation
InventorsMunehiko Nagatani, Teruo Jo, Hiroshi Yamazaki, Hideyuki Nosaka
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Abstract
An analog demultiplexer circuit includes a clock distribution circuit that outputs clock signals (CK1P and CK1N) and clock signals (CK2P and CK2N) complementary thereto, a track-and-hold circuit that holds analog input signals (VINP and VINN) in synchronization with the clock signals (CK1P and CK1N), and a track-and-hold circuit that holds the analog input signals (VINP and VINN) in synchronization with the clock signals (CK2P and CK2N).
Claims9
An analog demultiplexer circuit comprising:
- a clock distribution circuit configured to output first clock signals and second clock signals complementary thereto;
- a first track-and-hold circuit configured to hold analog input signals in synchronization with the first clock signals;
- and
- a second track-and-hold circuit configured to hold the analog input signals in synchronization with the second clock signals.
1 more element
An analog-to-digital conversion system comprising:
- a analog demultiplexer circuit, comprising:
- a clock distribution circuit configured to output first clock signals and second clock signals complementary thereto;
- a first track-and-hold circuit configured to hold analog input signals in synchronization with the first clock signals;
- and
- a second track-and-hold circuit configured to hold the analog input signals in synchronization with the second clock signals;
- a first analog-to-digital converter configured to convert a first analog output signal output from the first track-and-hold circuit of the analog demultiplexer circuit into a first digital signal;
- a second analog-to-digital converter configured to convert a second analog output signal output from the second track-and-hold circuit of the analog demultiplexer circuit into a second digital signal;
- a first addition circuit configured to add a first output signal of the first analog-to-digital converter and a second output signal of the second analog-to-digital converter;
- a subtraction circuit configured to subtract the second output signal of the second analog-to-digital converter from the first output signal of the first analog-to-digital converter;
- a folding processor configured to execute a folding processing of a third output signal of the subtraction circuit with a frequency of ½ of the first clock signals as a boundary;
- and
- a second addition circuit configured to add a fourth output signal of the first addition circuit and a sixth output signal of the folding processor.
9 more elements
Dependencies are inferred from the claim text.