Semiconductor integrated circuit

A semiconductor circuit including a data converter that outputs a digital output signal corresponding to a measured signal, the semiconductor circuit comprising:

• an analog circuit that quantizes the measured signal inputted;
• and
• a digital circuit that outputs the digital output signal,
• wherein the analog circuit includes:
• a correction element group including one or more correction elements each for correcting nonlinearity that occurs during a process of converting the measured signal into the digital output signal in the analog circuit;
• and
• a test element group including one or more test elements for testing the one or more correction elements,
• the digital circuit tests the correction element group using the test element group,
• the digital circuit includes:
• a self-diagnostic code generation circuit that generates a self-diagnostic code for (i) enabling or disabling each of the one or more correction elements included in the correction element group and (ii) enabling or disabling each of the one or more test elements included in the test element group;
• an error detection circuit that detects, as an error signal, a difference between a quantizer output signal of the analog circuit and a predetermined threshold value, the quantizer output signal being outputted in response to the self-diagnostic code;
• and
• a self-diagnostic circuit that generates a self-diagnostic signal indicating a diagnostic result of the correction element group, based on the error signal,
• the self-diagnostic code includes a first fixed code, a second fixed code, and an optimum code,
• the one or more correction elements are three or more correction elements,
• the first fixed code is for (i) enabling a single correction element selected as a test target from the correction element group and (ii) disabling other correction elements included in the correction element group and the one or more test elements,
• the optimum code is for minimizing the error signal relative to the first fixed code and is generated by binary search,
• the measured signal is a differential signal including a first polarity signal and a second polarity signal,
• the correction element group includes a first element group connected to a transmission path for the first polarity signal, and a second element group connected to a transmission path for the second polarity signal,
• the first fixed code corresponds to the first element group and is for disabling the second element group,
• the second fixed code is for (i) disabling a single correction element selected as a test target from the first element group, (ii) enabling, among other correction elements included in the first element group, a correction element having a weight smaller than a weight of the single correction element selected, and (iii) enabling the one or more test elements,
• the optimum code corresponds to the second element group and is for disabling the first element group, and
• the self-diagnostic circuit:
• calculates a first integrated value by integrating the error signal corresponding to a combination of the first fixed code and the optimum code;
• calculates a second integrated value by integrating the error signal corresponding to a combination of the second fixed code and the optimum code;
• and
• determines a magnitude relationship between the first integrated value and the second integrated value, and determines the single correction element selected as the test target as being faulty when the magnitude relationship fails to satisfy a predetermined condition.

A semiconductor circuit including a data converter that outputs a digital output signal corresponding to a measured signal, the semiconductor circuit comprising:

• an analog circuit that quantizes the measured signal inputted;
• and
• a digital circuit that outputs the digital output signal,
• wherein the analog circuit includes:
• a correction element group including one or more correction elements each for correcting nonlinearity that occurs during a process of converting the measured signal into the digital output signal in the analog circuit;
• and
• a test element group including one or more test elements for testing the one or more correction elements,
• the digital circuit tests the correction element group using the test element group,
• the digital circuit includes:
• a self-diagnostic code generation circuit that generates a self-diagnostic code for (i) enabling or disabling each of the one or more correction elements included in the correction element group and (ii) enabling or disabling each of the one or more test elements included in the test element group;
• an error detection circuit that detects, as an error signal, a difference between a quantizer output signal of the analog circuit and a predetermined threshold value, the quantizer output signal being outputted in response to the self-diagnostic code;
• and
• a self-diagnostic circuit that generates a self-diagnostic signal indicating a diagnostic result of the correction element group, based on the error signal,
• the digital circuit causes the self-diagnostic circuit to self-diagnose each of the one or more correction elements included in the correction element group,
• the self-diagnostic code generation circuit has:
• an optimum correction code output mode for outputting an optimum correction code in response to the error signal so that a quantization error of the quantizer becomes minimum;
• and
• a logic inversion code output mode for outputting a logic inversion code obtained by logically inverting a first bit signal for controlling a single correction element selected as a test target from the correction element group, the first bit signal being included in the optimum correction code, and
• at time of testing, the digital circuit:
• enters the optimum correction code output mode, supplies the optimum correction code to the analog circuit, and generates a first error signal, based on the error signal from the error detection circuit;
• enters the logic inversion code output mode, supplies the logic inversion code to the analog circuit, and generates a second error signal, based on the error signal from the error detection circuit;
• and
• compares magnitudes of the first error signal and the second error signal, and performs a fault diagnosis on the single correction element selected as the test target.

A semiconductor circuit including a data converter that outputs a digital output signal corresponding to a measured signal, the semiconductor circuit comprising:

• an analog circuit that quantizes the measured signal inputted;
• and
• a digital circuit that outputs the digital output signal,
• wherein the analog circuit includes:
• a correction element group including one or more correction elements each for correcting nonlinearity that occurs during a process of converting the measured signal into the digital output signal in the analog circuit;
• and
• a test element group including one or more test elements for testing the one or more correction elements,
• the digital circuit tests the correction element group using the test element group,
• the digital circuit includes:
• a self-diagnostic code generation circuit that generates a self-diagnostic code for (i) enabling or disabling each of the one or more correction elements included in the correction element group and (ii) enabling or disabling each of the one or more test elements included in the test element group;
• an error detection circuit that detects, as an error signal, a difference between a quantizer output signal of the analog circuit and a predetermined threshold value, the quantizer output signal being outputted in response to the self-diagnostic code;
• and
• a self-diagnostic circuit that generates a self-diagnostic signal indicating a diagnostic result of the correction element group, based on the error signal,
• the digital circuit causes the self-diagnostic circuit to self-diagnose each of the one or more correction elements included in the correction element group,
• the self-diagnostic code generation circuit has a first weight test code output mode and a second weight test code output mode,
• in the first weight test code output mode, the self-diagnostic code generation circuit:
• sets a first bit signal to 1 or 0, the first bit signal being for controlling a first correction element selected as a test target from the correction element group;
• causes a second correction bit signal group to have an inverted logical value of the first bit signal, the second correction bit signal group being for controlling a correction element having an adjustment weight smaller than an adjustment weight of the first correction element;
• causes a test bit signal to have the inverted logical value of the first bit signal, the test bit signal being for controlling the one or more test elements;
• and
• outputs one or more other bit signals as one or more predetermined fixed signals,
• in the second weight test code output mode, the self-diagnostic code generation circuit:
• causes the first bit signal to have an inverted logical value when the first weight test code output mode is set;
• causes the second correction bit signal group to have the inverted logical value of the first bit signal;
• causes the test bit signal to have the inverted logical value of the first bit signal;
• and
• outputs one or more other bit signals as one or more predetermined fixed signals, and
• at time of testing, the digital circuit:
• enters the first weight test code output mode and generates a first error signal, based on the error signal from the error detection circuit;
• enters the second weight test code output mode and generates a second error signal, based on the error signal from the error detection circuit;
• and
• calculates a difference between the first error signal and the second error signal, and performs a weighted diagnosis on the correction element group.

A semiconductor circuit including a data converter that outputs a digital output signal corresponding to a measured signal, the semiconductor circuit comprising:

• an analog circuit that quantizes the measured signal inputted;
• and
• a digital circuit that outputs the digital output signal,
• wherein the analog circuit includes:
• a correction element group including one or more correction elements each for correcting nonlinearity that occurs during a process of converting the measured signal into the digital output signal in the analog circuit;
• and
• a test element group including one or more test elements for testing the one or more correction elements,
• the digital circuit tests the correction element group using the test element group,
• the digital circuit includes:
• a self-diagnostic code generation circuit that generates a self-diagnostic code for (i) enabling or disabling each of the one or more correction elements included in the correction element group and (ii) enabling or disabling each of the one or more test elements included in the test element group;
• an error detection circuit that detects, as an error signal, a difference between a quantizer output signal of the analog circuit and a predetermined threshold value, the quantizer output signal being outputted in response to the self-diagnostic code;
• and
• a self-diagnostic circuit that generates a self-diagnostic signal indicating a diagnostic result of the correction element group, based on the error signal,
• the digital circuit causes the self-diagnostic circuit to self-diagnose each of the one or more correction elements included in the correction element group,
• the data converter includes an input switch that switches a signal to be inputted to the data converter between the measured signal and the reference signal,
• the self-diagnostic code generation circuit has an optimum correction code output mode for outputting an optimum correction code so that a quantization error of the quantizer becomes minimum,
• at time of testing, the digital circuit:
• enters the optimum correction code output mode, selects a first reference signal using the input switch, and calculates the optimum correction code as a first optimum correction code;
• enters the optimum correction code output mode, selects a second reference signal using the input switch, and calculates the optimum correction code as a second optimum correction code;
• and
• calculates a difference between the first optimum correction code and the second optimum correction code, and performs a correction range diagnosis on the correction element group.