Calibration of a time-to-digital converter using a virtual phase-locked loop

A clock generation method comprising:

• generating at least one digital time code with a time-to-digital converter in response to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal;
• and
• generating the time-to-digital converter calibration signal with a phase locked loop configured to generate an error signal in response the at least one digital time code.

A clock product comprising:

• a clock generator including a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal, and configured to generate at least one digital time code, the clock generator further including a calibration circuit configured to generate the time-to-digital converter calibration signal, the calibration circuit including a phase-locked loop configured to generate an error signal in response the at least one digital time code;
• and
• a controller configured to provide configuration information to the clock generator.