Background offset calibration of a high-speed analog signal comparator

A system, comprising:

• an analog circuit;
• an analog signal comparator that compares outputs of the analog circuit, the analog signal comparator comprising a preamplifier stage and a decision latch that samples an output of the preamplifier stage to generate an output state of the analog signal comparator;
• a switching circuit that selectively couples outputs of the analog circuit to inputs of the preamplifier stage of the analog signal comparator;
• a state control logic that alternatively operates the system in a first phase in which the analog circuit acquires an input signal and the analog signal comparator is being calibrated, and a second phase in which an output of the analog circuit is compared by the analog signal comparator, wherein a sampling cycle comprises operating the system in the first phase and then the second phase, wherein in the first phase, the state control logic controls the switching circuit to disconnect the outputs of the analog circuit from the inputs of the preamplifier stage of the analog signal comparator, and wherein the switching circuit applies a common mode reference to the inputs of the preamplifier stage of the analog signal comparator;
• and
• an offset correction circuit that determines an offset correction change dependent on a history of states of an output of the decision latch of the analog signal comparator across multiple sampling cycles of the system, wherein an output of the offset correction circuit is coupled to an offset input of the decision latch of the analog signal comparator to adjust a threshold voltage of the decision latch in conformity with the history of the states of the output of the decision latch.