Delay locked loop including replica fine delay circuit and memory device including the same

A memory device, comprising:

• a clock signal delay circuit configured to receive a reference clock signal and to provide the reference clock signal to an output circuit;
• and
• a delay locked loop comprising a replica fine delay circuit configured to replicate a fine delay circuit, a variable delay circuit, and a replica delay circuit,
• wherein the variable delay circuit comprises a coarse delay circuit and the fine delay circuit,
• wherein the coarse delay circuit is configured to delay the reference clock signal to generate a first clock signal,
• wherein the fine delay circuit is configured to delay the first clock signal to generate a second clock signal,
• wherein the replica delay circuit is configured to delay the first clock signal to generate a fourth clock signal, and
• wherein the replica fine delay circuit is configured to delay the fourth clock signal to generates a fifth clock signal.

An operation method of a memory device, the operation method comprising:

• receiving, at a delay locked loop of the memory device, a reference clock signal;
• delaying, at a coarse delay circuit of the delay locked loop, the reference clock signal to generate a first clock signal;
• delaying, at the delay locked loop, the first clock signal to generate a second clock signal;
• adjusting, at the delay locked loop, a delay amount of a replica fine delay circuit of the delay locked loop based on the second clock signal;
• and
• synchronizing, at the delay locked loop, the first clock signal with the reference clock signal based on a result of the adjusting of the delay amount.