High resolution phase correcting circuit and phase interpolating device

A phase correcting circuit, comprising:

• a delay circuit configured to receive an input clock signal and to delay the input clock signal as much as a first delay time to output an output clock signal to a 0-th node;
• a load capacitor;
• and
• one or more fine tuning circuits connected in series between the 0-th node and the load capacitor;
• wherein each of the one or more fine tuning circuits includes an input terminal, a control terminal, and an output terminal;
• wherein the input terminal is connected with the 0-th node or an output terminal of a previous fine tuning circuit, the control terminal receives a control signal, and the output terminal is connected with an input terminal of a next fine tuning circuit or the load capacitor;
• wherein, in response to the control signal, a phase of the output clock signal is tuned as much as a second delay time shorter than the first delay time;
• wherein each of the one or more fine tuning circuits includes an amplifier;
• and
• wherein the input terminal corresponds to an input terminal of the amplifier, the control terminal corresponds to a power terminal of the amplifier, and the output terminal corresponds to an output terminal of the amplifier.

A phase interpolating device, comprising:

• a decoder configured to generate a first control signal and a second control signal based on a phase difference of a clock signal and a reference signal;
• a phase shift unit including a plurality of phase correction circuits connected in series;
• and
• a phase select unit;
• wherein each of the plurality of phase correction circuits includes:
• a delay circuit configured to receive an input clock signal and to delay the input clock signal as much as a first delay time to output an output clock signal to an output node;
• a first fine tuning circuit including a first terminal connected with the output node, a second terminal receiving the first control signal, and a third terminal;
• and
• a second fine tuning circuit including a fourth terminal connected with the third terminal, a fifth terminal receiving the second control signal, and a sixth terminal connected with a load capacitor;
• wherein, in response to the first control signal, the output clock signal is further delayed as much as a second delay time shorter than the first delay time;
• wherein, in response to the second control signal, the output clock signal is advanced as much as a third delay time shorter than the first delay time;
• and
• wherein the phase select unit is configured to determine whether to select, as a corrected clock signal, an output clock signal output from the delay circuit of each of the plurality of phase correction circuits, based on the phase difference.