Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism

An apparatus comprising:

• an AND gate comprising a majority gate or a minority gate having non-linear polar material, wherein the AND gate is to receive a multiplier and a multiplicand;
• a 1-bit full adder comprising a majority gate or a minority gate coupled to the AND gate, wherein the 1-bit full adder comprises non-linear polar material, and wherein the 1-bit full adder is to receive a sum input and a carry input;
• and
• a reset mechanism comprising logic to condition first terminals of capacitors of the AND gate and the 1-bit full adder, the capacitors comprising the non-linear polar material, wherein the reset mechanism is to reset second terminals of the capacitors during a reset phase separate from an evaluation phase, and wherein the reset mechanism is to apply a predetermined input to the multiplier, the multiplicand, the sum input, and the carry input during the reset phase.

A system comprising:

• a processor circuitry to execute one or more instructions;
• a communication interface communicatively coupled to the processor circuitry;
• and
• a memory coupled to the processor circuitry, wherein the processor circuitry comprises a multiplier circuitry which includes:
• a majority gate or a minority gate having non-linear polar material, wherein the majority gate or the minority gate is coupled to a NOR gate or a NAND gate;
• and
• a reset mechanism to a reset a set of nodes coupled to the non-linear polar material during a reset phase separate from an evaluation phase, wherein a node from the set of nodes is coupled to the NOR gate or the NAND gate, and wherein the NOR gate or the NAND gate is controllable by the reset mechanism.