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US 11,888,478 B2Granted
Methods and apparatus to perform CML-to-CMOS deserialization
AssigneeTexas Instruments Incorporated
InventorsNithin Sathisan Poduval, Abishek Manian, Roland Nii Ofei Ribeiro
Life of this patent
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Abstract
An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.
Claims6
An apparatus comprising:
- a first latch including a first latch input, a first latch clock input, and a first latch output, the first latch input coupled to a data input, the first latch clock input coupled to a first clock input;
- a first SR-Latch including a first SR-Latch input and a first SR-Latch output, the first SR-Latch input coupled to the first latch output;
- a second latch including a second latch input, a second latch clock input, and a second latch output, the second latch input coupled to the data input, the second latch clock input coupled to a second clock input;
- a second SR-Latch including a second SR-Latch input, the second SR-Latch input coupled to the second latch output;
- and
- a third latch including a third latch input and a third latch clock input, the third latch input coupled to the first SR-Latch output, the third latch clock input coupled to the second clock input.
3 more elements
Dependencies are inferred from the claim text.