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US 11,888,394 B2Granted
High-efficiency pulse width modulation for switching power converters
AssigneeDialog Semiconductor (UK) Limited
InventorsKevin Yi Cheng Chang, Kelly Consoer
Life of this patent
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Abstract
A switching power converter is provided with a one-shot bias boosting circuit that responds to a premature trip point to boost the performance of a linear comparator in a pulse width modulator. In a sense-amplifier based implementation of the comparator, a clock-edge generator boosts the performance of the sense amplifier at the premature trip point.
Claims8
A switching power converter pulse width modulator, comprising:
- an error signal generator configured to generate an error signal that is proportional to a difference between an output voltage and a reference voltage;
- a ramp signal generator configured to generate a ramp signal;
- a clock-edge generator configured to assert an enable signal for an enable period responsive to a level-shifted version of the error signal being equal to the ramp signal;
- and
- a sense-amplifier-based comparator configured to be enabled by the assertion of the enable signal during the enable period, wherein the sense-amplifier-based comparator is further configured to assert a comparator output signal responsive to the ramp signal being equal to the error signal only while the sense-amplifier-based comparator is enabled.
2 more elements
A switching power converter pulse width modulator, comprising:
- an error signal generator configured to generate an error signal that is proportional to a difference between an output voltage and a reference voltage;
- a ramp signal generator configured to generate a ramp signal;
- a clock-edge generator configured to assert an enable signal for an enable period responsive to a level-shifted version of the ramp signal being equal to the error signal, wherein the level-shifted version of the ramp signal is greater than the ramp signal by an offset voltage;
- and
- a sense-amplifier-based comparator configured to be enabled by the assertion of the enable signal during the enable period, wherein the sense-amplifier-based comparator is further configured to assert a comparator output signal responsive to the ramp signal being equal to the error signal only while the sense-amplifier-based comparator is enabled.
2 more elements
Dependencies are inferred from the claim text.