Systems and methods for making solar panels or components thereof
AssigneeDual Helios Semiconductor Equipment Company, Inc.
InventorLawrence Chung-Lai Lei
Life of this patent
Estimating the term…
Abstract
A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.
Claims27
A wafer processing method, comprising:
- providing a frame comprising a frame opening, wherein a membrane with a membrane opening is coupled to the frame covering at least a part the frame opening, wherein a wafer is coupled to the membrane covering the membrane opening;
- maintaining the frame, the membrane, and the wafer vertically;
- forming a first I-layer over a first surface of the wafer while the wafer is oriented vertically;
- forming a second I-layer over a second surface of the wafer while the wafer is oriented vertically, the second surface of the wafer being opposite from the first surface;
- forming a N-layer over the first I-layer while the wafer is oriented vertically;
- and
- forming a P-layer over the second I-layer while the wafer is oriented vertically.
A wafer processing method, comprising:
- providing a frame comprising a frame opening, wherein a membrane with a membrane opening is coupled to the frame covering at least a part the frame opening, wherein a wafer is coupled to the membrane covering the membrane opening;
- maintaining the frame, the membrane, and the wafer vertically;
- forming a first I-layer over a first surface of the wafer while the wafer is oriented vertically;
- forming a second I-layer over a second surface of the wafer while the wafer is oriented vertically, the second surface of the wafer being opposite from the first surface;
- forming a N-layer over the first I-layer while the wafer is oriented vertically;
- forming a P-layer over the second I-layer while the wafer is oriented vertically;
- forming a first conductive layer over the first surface of the wafer;
- forming a second conductive layer over the second surface of the wafer;
- forming a first conductive line over the first surface of the wafer while the wafer is coupled to the membrane, the first conductive line connecting to surfaces of the first conductive layer;
- and
- forming a second conductive line over the second surface of the wafer while the wafer is coupled to the membrane, the second conductive line connecting to surfaces of the second conductive layer.
A wafer processing method, comprising:
- providing a frame comprising a frame opening, wherein a membrane with a membrane opening is coupled to the frame covering at least a part the frame opening, wherein a wafer is coupled to the membrane covering the membrane opening;
- maintaining the frame, the membrane, and the wafer vertically;
- forming a first I-layer over a first surface of the wafer while the wafer is oriented vertically;
- forming a second I-layer over a second surface of the wafer while the wafer is oriented vertically, the second surface of the wafer being opposite from the first surface,
- forming a N-layer over the first I-layer while the wafer is oriented vertically;
- and
- forming a P-layer over the second I-layer while the wafer is oriented vertically;
- wherein the membrane comprises an additional membrane opening, wherein an additional wafer is coupled to the membrane covering the additional membrane opening.
A wafer processing method, comprising:
- providing a frame comprising a frame opening, wherein a membrane with a membrane opening is coupled to the frame covering at least a part the frame opening, wherein a wafer is coupled to the membrane covering the membrane opening;
- maintaining the frame, the membrane, and the wafer vertically;
- forming a first I-layer over a first surface of the wafer while the wafer is oriented vertically;
- forming a second I-layer over a second surface of the wafer while the wafer is oriented vertically, the second surface of the wafer being opposite from the first surface;
- forming a N-layer over the first I-layer while the wafer is oriented vertically;
- forming a P-layer over the second I-layer while the wafer is oriented vertically;
- and
- providing texturing treatment for the wafer;
- wherein the method further comprises, before the act of providing texturing treatment, coupling the membrane with a first isolation grid, wherein the first isolation grid is coupled to a first surface of the membrane.
Dependencies are inferred from the claim text.