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US 11,888,074 B2Granted
Flash memory device with three-dimensional half flash structure and methods for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Chu Lin, Chi-Chung Jen, Yi-Ling Liu, Wen-Chih Chiang, Keng-Ying Liao, Huai-Jen Tung
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Abstract
A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
Claims20
A method of making a flash memory device, comprising:
- depositing a continuous tunnel dielectric layer over a substrate;
- depositing a continuous floating gate layer over the continuous tunnel dielectric layer;
- depositing a continuous control gate dielectric layer over the continuous floating gate layer;
- depositing a continuous control gate layer over the continuous control gate dielectric layer;
- patterning the continuous tunnel dielectric layer, the continuous floating gate layer, the continuous control gate dielectric layer and the continuous control gate layer by performing a first anisotropic etch process to form a patterned tunnel dielectric layer, a floating gate electrode, a patterned control gate dielectric layer and a control gate electrode;
- further patterning the control gate electrode by performing a second anisotropic etch process to expose a surface of the patterned control gate dielectric layer and form a smaller length control gate electrode such that the smaller length control gate electrode has a length along a major axis of the smaller length control gate electrode that is less than a length of the floating gate electrode along a major axis of the floating gate electrode;
- forming a source region and a drain region in the substrate;
- and
- forming an electrical contact on the exposed surface of the patterned control gate dielectric layer, wherein the exposed surface of the control gate dielectric layer is over a channel region located between the source region and the drain region.
6 more elements
A method for forming a flash memory cell, comprising:
- forming a layer stack including a continuous tunnel dielectric layer, a continuous floating gate layer, a continuous control gate dielectric layer, a continuous control gate layer over a semiconductor substrate;
- patterning the layer stack, wherein a patterned portion of the layer stack comprises a stack of patterned layers including a tunnel dielectric layer, a floating gate electrode, a control gate dielectric layer, and a control gate electrode;
- reducing a size of the control gate electrode by etching a portion of the control gate electrode to expose a surface of the control gate dielectric layer, wherein a lateral extent of the control gate electrode along a horizontal direction becomes less than a lateral extent of the control gate dielectric layer along the horizontal direction;
- forming a source region and a drain region in an upper portion of the semiconductor substrate, wherein the source region and the drain region are laterally spaced apart along the horizontal direction;
- and
- forming an electrical contact on the exposed surface of the control gate dielectric layer, wherein the exposed surface of the control gate dielectric layer is over a channel region located between the source region and the drain region.
3 more elements
A method for forming a flash memory cell, comprising:
- forming a stack including a tunnel dielectric layer, a floating gate electrode, a control gate dielectric layer, and a control gate electrode over a semiconductor substrate, wherein each sidewall of the stack vertically extends from a top surface of the semiconductor substrate to an edge of a top surface of the control gate electrode within a respective vertical plane;
- reducing a size of the control gate electrode by etching a portion of the control gate electrode to expose a surface of the control gate dielectric layer, wherein a lateral extent of the control gate electrode along a horizontal direction becomes less than a lateral extent of the control gate dielectric layer along the horizontal direction;
- and
- forming a source region and a drain region in an upper portion of the semiconductor substrate, wherein the source region and the drain region are laterally spaced apart along the horizontal direction;
- and
- forming an electrical contact on the exposed surface of the control gate dielectric layer, wherein the exposed surface of the control gate dielectric layer is over a channel region located between the source region and the drain region.
3 more elements
Dependencies are inferred from the claim text.