Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsWeonhong Kim, Wandon Kim, Hyeonjun Baek, Sangjin Hyun
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Abstract
A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.
Claims20
A semiconductor device, comprising:
- a substrate including an active pattern;
- a plurality of semiconductor patterns stacked on the active pattern, the plurality of semiconductor patterns being vertically spaced apart from each other;
- a source/drain pattern on the active pattern and connected to the plurality of semiconductor patterns;
- a gate electrode on the plurality of semiconductor patterns;
- and
- a ferroelectric pattern interposed between the plurality of semiconductor patterns and the gate electrode,
- wherein the ferroelectric pattern contacts top, bottom and side surfaces of each of the plurality of semiconductor patterns.
A semiconductor device, comprising:
- a substrate including an active pattern;
- a plurality of semiconductor patterns stacked on the active pattern, the plurality of semiconductor patterns being vertically spaced apart from each other;
- a source/drain pattern on the active pattern and connected to the plurality of semiconductor patterns;
- a gate electrode on the plurality of semiconductor patterns;
- and
- a ferroelectric pattern interposed between the plurality of semiconductor patterns and the gate electrode, and between the source/drain pattern and the gate electrode,
- wherein the ferroelectric pattern directly covers a surface of the source/drain pattern.
A semiconductor device, comprising:
- a substrate including an active pattern;
- a plurality of semiconductor patterns stacked on the active pattern, the plurality of semiconductor patterns being vertically spaced apart from each other;
- a source/drain pattern on the active pattern and connected to the plurality of semiconductor patterns;
- a gate electrode on the plurality of semiconductor patterns, the gate electrode including a metal nitride pattern in a space between adjacent ones of the plurality of semiconductor patterns;
- and
- a ferroelectric pattern surrounding top, bottom and side surfaces of the metal nitride pattern within the space.
Dependencies are inferred from the claim text.