Extended-drain metal-oxide-semiconductor devices with a silicon-germanium layer beneath a portion of the gate

A structure for an extended-drain metal-oxide-semiconductor device, the structure comprising:

• a semiconductor substrate comprising a first semiconductor material;
• a first well in the semiconductor substrate;
• a second well in the semiconductor substrate, the second well adjoining the first well along an interface;
• a source region and a drain region in the semiconductor substrate, the source region positioned in the first well, and the drain region positioned in the second well;
• a semiconductor layer positioned on the semiconductor substrate, the semiconductor layer comprising a second semiconductor material that differs in composition from the first semiconductor material, and the semiconductor layer having an edge that is approximately aligned with the interface;
• a gate electrode positioned in a lateral direction between the source region and the drain region, the gate electrode including a first section positioned on a first portion of the semiconductor layer and a second section positioned on the semiconductor substrate;
• and
• a gate dielectric including a first portion in direct contact with the first portion of the semiconductor layer and a second portion in direct contact with the semiconductor substrate, the first portion of the gate dielectric positioned in a vertical direction between the first section of the gate electrode and the first portion of the semiconductor layer, and the second portion of the gate dielectric positioned in the vertical direction between the second section of the gate electrode and the semiconductor substrate,
• wherein the first portion of the semiconductor layer and the first section of the gate electrode are positioned over a portion of the first well and over a portion of the second well.

A method of forming a structure for an extended-drain metal-oxide-semiconductor device, the method comprising:

• forming a first well in a semiconductor substrate, wherein the semiconductor substrate comprises a first semiconductor material;
• forming a second well in the semiconductor substrate, wherein the second well adjoins the first well along an interface;
• forming a semiconductor layer positioned on the semiconductor substrate, wherein the semiconductor layer comprises a second semiconductor material that differs in composition from the first semiconductor material;
• forming a source region and a drain region in the semiconductor substrate, wherein the source region is positioned in the first well, and the drain region is positioned in the second well;
• forming a gate electrode positioned in a lateral direction between the source region and the drain region, wherein the gate electrode includes a first section positioned on a first portion of the semiconductor layer and a second section positioned over the semiconductor substrate;
• and
• forming a gate dielectric including a first portion in direct contact with the first portion of the semiconductor layer and a second portion in direct contact with the semiconductor substrate, the first portion of the gate dielectric positioned in a vertical direction between the first section of the gate electrode and the first portion of the semiconductor layer, and the second portion of the gate dielectric positioned in the vertical direction between the second section of the gate electrode and the semiconductor substrate,
• wherein the first portion of the semiconductor layer and the first section of the gate electrode are positioned over a portion of the first well and over a portion of the second well.