US 11,888,049 B2 · Dielectric isolation structure for multi-gate transistors

Abstract

Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.

Claims20

Dependent claims

A semiconductor structure, comprising:

a first dielectric fin and a second dielectric fin;
a plurality of channel members disposed between the first dielectric fin and the second dielectric fin;
and
a gate structure disposed between the first dielectric fin and the second dielectric fin and wrapping around each of the plurality of channel members,
wherein each of the first dielectric fin and the second dielectric fin comprises a base feature and a helmet feature over the base feature,
wherein the helmet feature comprises a bottom width and a top width greater than the bottom width such that the helmet feature comprises a tapered profile.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/077,714Filed 8 Dec 2022 · division

Priority

25 Jun 2021

Published

US 2023/0098409 A130 Mar 2023

Granted

30 Jan 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/0191
Of FETs having stacked nanowire, nanosheet or nanoribbon channels: forming stacked channels, e.g. changing their shapes or sizes
H10D 30/506
Wherein the stacked channels have different properties: having different thicknesses, sizes or shapes
H10D 30/6211
Fin field-effect transistors [FinFET]: having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates

Family

Application17/359,105Parent of this division · filed 25 Jun 2021

US 2023/0098409 A1Pre-grant publication · published 30 Mar 2023

US 11,532,733 B1Parent of this division

US 2022/0416058 A1Published application

US 11,888,049 B2This patent

From the US filing history. Foreign family members aren’t listed.

Dielectric isolation structure for multi-gate transistors

Life of this patent

Dielectric isolation structure for multi-gate transistors

Life of this patent

Abstract

Claims20