Gate oxide for nanosheet transistor devices

A semiconductor device, comprising:

• at least one nanosheet transistor structure disposed on a semiconductor substrate, the at least one nanosheet transistor structure including:
• a first nanosheet stack having a plurality of first channel layers;
• a first source region and a first drain region;
• a first metal gate disposed about the at least one nanosheet transistor structure;
• and
• an oxide layer disposed relative to the first metal gate, the oxide layer comprising one or more segments disposed between the first metal gate and the first source and first drain regions;
• and
• a second nanosheet transistor structure disposed on the semiconductor substrate, the second nanosheet transistor structure including a second nanosheet stack having a plurality of second channel layers;
• wherein a first channel layer that is closest to the semiconductor substrate among the plurality of first channel layers is spaced farther from a top surface of the semiconductor substrate than a second channel layer that is closest to the semiconductor substrate among the plurality of second channel layers;
• wherein the first nanosheet stack further includes a plurality of dielectric spacers disposed between the one or more segments of the oxide layer and the first source and first drain regions;
• and
• wherein a portion of the one or more segments of the oxide layer contacts at least one of the first source and first drain regions.

A semiconductor device, comprising:

• first and second nanosheet FET devices positioned on a semiconductor substrate, each of the first and second nanosheet FET devices respectively including a plurality of first channel members and a plurality of second channel members above the semiconductor substrate, a first gate structure and a second gate structure, a first source region and a second source region, and a first drain region and a second drain region;
• wherein a number of the plurality of first channel members is greater than a number of the plurality of second channel members;
• wherein the second nanosheet FET device includes an oxide layer having one or more oxide segments, the one or more oxide segments disposed between adjacent ones of the plurality of second channel members, between the second gate structure and the semiconductor substrate, and between the second gate structure and the second source and second drain regions;
• wherein a second channel member that is closest to the semiconductor substrate among the plurality of second channel members is spaced farther from a top surface of the semiconductor substrate than a first channel member that is closest to the semiconductor substrate among the plurality of first channel members;
• wherein the second nanosheet FET device further includes a plurality of dielectric spacers disposed between the one or more oxide segments and the second source and second drain regions;
• and
• wherein a portion of the one or more oxide segments contacts at least one of the second source and second drain regions.