Integrated dipole flow for transistor

An electronic device comprising:

• a source region, a drain region and a channel separating the source region and drain region;
• a dipole region on a top surface of the channel, the dipole region comprising an interlayer dielectric, a high-κ dielectric material, and a dipole layer, the dipole layer deposited by atomic layer deposition (ALD) at a temperature in a range of from 200° C. to about 500° C. of alternating cycles of a hafnium precursor and a second precursor, the dipole layer comprising one or more of hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN);
• a gate on the dipole region;
• and
• a capping layer on the dipole region.