Three-dimensional semiconductor memory devices and methods of fabricating the same

A data storage system comprising:

• a plurality of semiconductor memory devices;
• and
• a controller that is configured to control the semiconductor memory devices,
• wherein each of the semiconductor memory devices comprises:
• a stacked structure comprising a plurality of electrodes and insulating patterns that are stacked alternately and repeatedly on a substrate;
• a semiconductor pattern penetrating the stacked structure;
• and
• a tunneling layer, a charge storage layer, a capping layer and a blocking insulation layer between the semiconductor pattern and the electrodes,
• wherein each of the insulating patterns has a first sidewall adjacent the semiconductor pattern and a second sidewall opposite the first sidewall,
• wherein the tunneling layer, the charge storage layer, and the capping layer extend along the first sidewalls of the respective insulating patterns,
• wherein the capping layer comprises a silicon oxide layer,
• wherein the blocking insulation layer consists of at least one of an aluminum oxide layer, a hafnium oxide layer, a zirconium oxide layer, a tantalum oxide layer, and a titanium oxide layer, and
• wherein the blocking insulation layer includes a first portion extending along the second sidewalls of the insulating patterns.

A semiconductor memory device comprising:

• a stacked structure comprising a plurality of electrodes and insulating patterns that are stacked alternately and repeatedly on a substrate;
• a semiconductor pattern penetrating the stacked structure;
• and
• a tunneling layer, a charge storage layer, a capping layer and a blocking insulation layer between the semiconductor pattern and the electrodes,
• wherein each of the insulating patterns has a first sidewall adjacent the semiconductor pattern and a second sidewall opposite the first sidewall,
• wherein the tunneling layer, the charge storage layer, and the capping layer extend along the first sidewalls of the respective insulating patterns,
• wherein the capping layer comprises a silicon oxide layer,
• wherein the blocking insulation layer comprises a high-k dielectric layer, and
• wherein the blocking insulation layer includes a first portion extending along the second sidewalls of the insulating patterns.