SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof

A silicon-on-insulator (SOI) lateral homogenization field high voltage power semiconductor device, comprising

• a type I conductive semiconductor substrate, a type I conductive well region, a type I conductive source heavily doped region, a type II conductive drift region, a type II conductive well region, a type II conductive source heavily doped region, a type II conductive drain heavily doped region, a first dielectric oxide layer, a second dielectric oxide layer, a third dielectric oxide layer;
• a buried dielectric layer, polysilicon electrodes, a control gate polysilicon electrode, a source metal, and a drain metal;
• wherein the buried dielectric layer is located above the type I conductive semiconductor substrate, the type II conductive drift region is above the buried dielectric layer, the type I conductive well region is located on a left side of the type II conductive drift region, the type I conductive source heavily doped region and the type II conductive source heavily doped region are located in the type I conductive well region, the type II conductive well region is located on a right side of the type II conductive drift region, and the type II conductive drain heavily doped region is located in the type II conductive well region;
• the second dielectric oxide layer is located above the type I conductive well region, wherein a left end of the second dielectric oxide layer is in contact with the type II conductive source heavily doped region, and a right end of the second dielectric oxide layer is in contact with the type II conductive drift region;
• the third dielectric oxide layer is located on an upper surface of the type II conductive drift region between the second dielectric oxide layer and the type II conductive drain heavily doped region;
• the control gate polysilicon electrode covers an upper surface of the second dielectric oxide layer and partially extends to an upper surface of the third dielectric oxide layer;
• and
• the first dielectric oxide layer and the polysilicon electrodes constitute vertical floating field plates extending longitudinally, and a number of the vertical floating field plates is one or more;
• adjacent vertical floating field plates in source-drain directions are staggered;
• the vertical floating field plates are periodically distributed in the entire type II conductive drift region, forming a voltage-sustaining layer having a plurality of equipotential floating trenches;
• the plurality of equipotential floating trenches are connected with the buried dielectric layer, and the polysilicon electrodes are inserted into the buried dielectric layer, but do not penetrate the buried dielectric layer;
• a longitudinal spacing and a transverse spacing of the adjacent vertical floating field plates are equal;
• a transverse direction is the source-drain direction, and a longitudinal direction is perpendicular to the source-drain direction.