US 11,887,987 B2Granted

Semiconductor wafer with devices having different top layer thicknesses

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsGulbagh Singh, Kuan-Liang Liu, Wang Po-Jen, Kun-Tsang Chuang, Hsin-Chi Chen

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Abstract

A circuit includes a base silicon layer, a base oxide layer, a first top silicon layer, a second top silicon layer, a first semiconductor device, and a second semiconductor device. The base oxide layer is formed over the base silicon layer. The first top silicon layer is formed over a first region of the base oxide layer and has a first thickness. The second top silicon layer is formed over a second region of the base oxide layer and has a second thickness less than the first thickness. The first semiconductor device is formed over the first top silicon layer and the second semiconductor device is formed over the second top silicon layer. The ability to fabricate a top silicon layers with differing thicknesses can provide a single substrate having devices with different characteristics, such as having both fully depleted and partially depleted devices on a single substrate.

Claims20

Dependent claims

A circuit comprising:

a base silicon layer;
a base oxide layer formed over the base silicon layer;
a first top silicon layer formed over a first region of the base oxide layer, the first top silicon layer having a first thickness;
a second top silicon layer formed over a second region of the base oxide layer, the second top silicon layer having a second thickness that is less than the first thickness;
a first semiconductor device formed over the first top silicon layer;
a second semiconductor device formed over the second top silicon layer;
a first added oxide formed on the base oxide layer, the first top silicon layer contacting a top surface of the first added oxide and a bottom surface of the first semiconductor device;
and
a second added oxide formed on the base oxide layer, the second top silicon layer contacting a top surface of the second added oxide and a bottom surface of the second semiconductor device;
wherein a third thickness of the first added oxide is less than a fourth thickness of the second added oxide;
wherein a sum of the first thickness of the first top silicon layer and the third thickness of the first added oxide is equal to a sum of the second thickness of the second top silicon layer and the fourth thickness of second added oxide;
and
wherein a height of a bottom surface of the first added oxide is the same as a height of a bottom surface of the second added oxide.

10 more elements

A circuit comprising:

a base silicon layer;
a base oxide layer formed over the base silicon layer;
a first top silicon layer formed over a first region of the base oxide layer, the first top silicon layer having a first thickness;
a second top silicon layer formed over a second region of the base oxide layer, the second top silicon layer having a second thickness that is less than the first thickness;
a first semiconductor device formed over the first top silicon layer;
a second semiconductor device formed over the second top silicon layer, wherein:
the first semiconductor device comprises a partially depleted device and the first thickness is between 500 and 3000 angstroms, and the second semiconductor device comprises a fully depleted device and the second thickness is between 50 and 500 angstroms;
a first added oxide formed on the base oxide layer, the first top silicon layer contacting a top surface of the first added oxide and a bottom surface of the first semiconductor device;
and
a second added oxide formed on the base oxide layer, the second top silicon layer contacting a top surface of the second added oxide and a bottom surface of the second semiconductor device;
wherein a third thickness of the first added oxide is less than a fourth thickness of the second added oxide;
wherein a sum of the first thickness of the first top silicon layer and the third thickness of the first added oxide is equal to a sum of the second thickness of the second top silicon layer and the fourth thickness of second added oxide;
and
wherein a height of a bottom surface of the first added oxide is a same as a height of a bottom surface of the second added oxide.

11 more elements

A circuit comprising:

a base silicon layer;
a base oxide layer formed over the base silicon layer;
a first top silicon layer formed over a first region of the base oxide layer, the first top silicon layer having a first thickness;
a second top silicon layer formed over a second region of the base oxide layer, the second top silicon layer having a second thickness that is less than the first thickness;
a third top silicon layer formed over a third region of the base oxide layer, the third top silicon layer having a fifth thickness that is less than the second thickness;
a first semiconductor device formed over the first top silicon layer;
a second semiconductor device formed over the second top silicon layer;
and
a third semiconductor device formed over the third top silicon layer;
a first added oxide formed on the base oxide layer, the first top silicon layer contacting a top surface of the first added oxide and a bottom surface of the first semiconductor device;
and
a second added oxide formed on the base oxide layer, the second top silicon layer contacting a top surface of the second added oxide and a bottom surface of the second semiconductor device;
wherein a third thickness of the first added oxide is less than a fourth thickness of the second added oxide;
wherein a sum of the first thickness of the first top silicon layer and the third thickness of the first added oxide is equal to a sum of the second thickness of the second top silicon layer and the fourth thickness of second added oxide;
and
wherein a height of a bottom surface of the first added oxide is a same as a height of a bottom surface of the second added oxide.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/827,636Filed 27 May 2022 · division
Priority: 17 Apr 2020
Published: US 2022/0285403 A18 Sep 2022
Granted: 30 Jan 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 86/201
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…
H10D 86/01
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…
H10P 14/3411
Being Group IVA materials: silicon, silicon germanium or germanium
H10P 50/642
Of semiconductor materials: chemical etching

Family

Application16/851,345Parent of this division · filed 17 Apr 2020
US 2022/0285403 A1Pre-grant publication · published 8 Sep 2022
US 11,348,944 B2Parent of this division
US 2021/0327902 A1Published application
US 11,887,987 B2This patent

From the US filing history. Foreign family members aren’t listed.