Complementary transistor and semiconductor device
AssigneeSony Group Corporation
InventorsHidetoshi Oishi, Koichi Matsumoto, Kazuyuki Tomida
Life of this patent
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Abstract
A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211,212 respectively.
Claims20
A complementary transistor, comprising:
- a semiconductor substrate;
- a first transistor including:
- a first control electrode;
- a first active region located below the first control electrode;
- a first A extension region extending from one end of the first active region;
- a first B extension region extending from the other end of the first active region;
- and
- a buffer layer provided between the first control electrode and the semiconductor substrate;
- and
- a second transistor including:
- a second control electrode;
- a second active region located below the second control electrode;
- a second A extension region extending from one end of the second active region;
- and
- a second B extension region extending from the other end of the second active region.
A complementary transistor, comprising:
- a semiconductor substrate;
- a first transistor including:
- a first control electrode;
- a first boundary region located below the first control electrode and formed by a first B layer;
- a first A extension layer extending from one end of the first boundary region;
- a first B extension layer of the first B layer extending from the other end of the first boundary region;
- a second transistor including:
- a second control electrode;
- a second boundary region located below the second control electrode and formed by
- a second B layer;
- a second A extension layer extending from one end of the second boundary region;
- and
- a second B extension layer of the second B layer extending from the other end of the second boundary region;
- a first element isolation region provided between the semiconductor substrate and the first boundary region,
- wherein the first element isolation region is provided under the first B layer and the first B extension layer;
- and
- a second element isolation region provided between the semiconductor substrate and the second boundary region,
- wherein the second element isolation region is provided under the second B layer and the second B extension layer.
A complementary transistor, comprising:
- a semiconductor substrate;
- a first transistor including:
- a first control electrode;
- a first boundary region located below the first control electrode and formed by a first
- B layer;
- a first A extension layer extending from one end of the first boundary region;
- a first B extension layer of the first B layer extending from the other end of the first boundary region;
- a second transistor including:
- a second control electrode;
- a second boundary region located below the second control electrode and formed by a second B layer;
- a second A extension layer extending from one end of the second boundary region;
- and
- a second B extension layer of the second B layer extending from the other end of the second boundary region;
- a first element isolation region provided within the semiconductor substrate, wherein the first element isolation region is provided under the first B layer and the first B extension layer;
- and
- a second element isolation region provided within the semiconductor substrate,
- wherein the second element isolation region is provided under the second B layer and the second B extension layer.
Dependencies are inferred from the claim text.